Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

Abstract: A method for performing a sense and restore operation in a multilevel DRAM is described. The method describes the selective enabling of the sense amplifiers to operate at predetermined sensing thresholds. The multilevel DRAM stores two bits per cell using a four-voltage-level-per-cell system. Folded bitlines are divided into sub-bitlines each having dedicated sense amplifiers. The sense amplifiers are selectively enabled to operate at predetermined sensing thresholds to thereby greatly simplify the sense and restore operations. The circuit has standard CMOS bitline sense amplifier transistors connected thereto with pull down transistors that may be selectively enabled by switch signals. The length and width of these pull down transistors are varied to thereby effect the switching threshold of the sense amplifier.

Abstract: A method for performing a sense and restore operation in a multilevel DRAM is described. The method describes the selective enabling of the sense amplifiers to operate at predetermined sensing thresholds. The multilevel DRAM stores two bits per cell using a four-voltage-level-per-cell system. Folded bitlines are divided into sub-bitlines each having dedicated sense amplifiers. The sense amplifiers are selectively enabled to operate at predetermined sensing thresholds to thereby greatly simplify the sense and restore operations. The circuit has standard CMOS bitline sense amplifier transistors connected thereto with pull down transistors that may be selectively enabled by switch signals. The length and width of these pull down transistors are varied to thereby effect the switching threshold of the sense amplifier.

Abstract: Cryptographic methods are disclosed, which allow a prover party, who holds a number of secrets, to demonstrate satisfiable formulas of propositional logic, wherein the atomic propositions are linear relations between the secrets. The demonstration reveals no more information than is contained in the formula itself. Some implementations allow an unlimited number of such demonstrations to be made, without revealing any additional information about the secrets, whereas other implementations ensure that the secrets, or some of the secrets, will be revealed, if a demonstration is performed more than a predetermined number of times. The demonstrations may be zero-knowledge proofs, or signed proofs.

Abstract: A wideband slot-loop antenna is described which comprises a generally planar loop element having a generally rectangular outer perimeter and a slot defining an inner perimeter, the mid portion of the slot-loop structure providing a major radiation portion of the antenna; a loading structure extending from one end of the slot, the loading structure for top loading the radiation portion; and an impedance matching portion for coupling a feed to the major radiation portion. The antenna also includes distributed matching patches. The distributed matching patches realize extra wideband performance. The antennas in the present invention are suitable for various wireless communications, such as PCS, Cellular Telephone, wireless data and computer network.

Abstract: The present invention relates to a system for providing a communication network, comprising: an intranet-connected server having input and access capabilities; a means on the server for receiving instructions input from a first user and for creating a dedicated intranet site based on the received instructions; means to communicate existence of the dedicated intranet site to a nominated second user; means to access contents of the dedicated intranet site by the second user via a web-browser installed on the second user; and means to store information in the dedicated intranet site input via a web-browser installed at the first or the second user.

Abstract: A semiconductor device having a self test circuit including an embedded dynamic random access memory array for storing data, a self test controller for internally generating test data patterns and expected resulting data and for comparing the expected resulting data with actual resulting data, test interface circuitry for loading the test data patterns into the memory and reading back the actual resulting data from the memory, means for selectively programming a voltage level to be applied to a selected cell plate of the memory according to predetermined test requirements and means for storing an address of a defective memory cell. In addition, the semiconductor device includes means for repairing a defective memory row or column in response to a signal received from the self test controller.

Abstract: A method for performing a sense and restore operation in a multilevel DRAM is described. The method describes the selective enabling of the sense amplifiers to operate at predetermined sensing thresholds. The multilevel DRAM stores two bits per cell using a four-voltage-level-per-cell system. Folded bitlines are divided into sub-bitlines each having dedicated sense amplifiers. The sense amplifiers are selectively enabled to operate at predetermined sensing thresholds to thereby greatly simplify the sense and restore operations. The circuit has standard CMOS bitline sense amplifier transistors connected thereto with pull down transistors that may be selectively enabled by switch signals. The length and width of these pull down transistors are varied to thereby effect the switching threshold of the sense amplifier.

Abstract: This invention provides a data bit redundancy method and apparatus that permits the replacement of faulty bitlines on a data bit basis as opposed to a column address basis. This invention provides a semiconductor memory device having memory cells arranged in columns and rows. Normal local data lines are connected to a global data line via a first switch. A redundant memory data line is connected to the global data line via a second switch. A control generating first and second control signals are coupled to the respective first and second switches for operating the switch in response to a status of a fuse component, whereby when the fuse is intact the normal data lines are connected to the global data line and when the rise is blown the redundant data lines are connected to the global data line, thus not requiring additional redundancy address decoding circuitry.

Abstract: This invention describes a column redundancy arrangement in a DRAM that minimizes the timing difference between a normal and a redundant column path. A semiconductor memory device comprises memory elements arranged in rows and columns. The memory elements are accessed by energizing one or more rows and columns. A first and a second group of normal column drivers are provided for energizing associated normal memory columns in response to respective ones of column select signals. Further, a first and second redundant column driver are provided for energizing associated redundant memory columns upon receipt of a column select signal along a redundancy select line. A plurality of programmable switches are associated with the normal column drivers, for selectively steering respective ones of the column select signals to associated column drivers or the first or second of the redundant column drivers.

Abstract: The invention discloses a synchronous DRAM having memory elements arranged in rows and columns, the memory elements being accessible by decoding a memory address applied thereto, normal column drivers for activating appropriate memory elements in response to decoded column addresses signals; redundant column drivers distributed throughout memory banks and flexibly selectable to replace faulty columns within multiple blocks within a bank; and switch means for selectively activating the redundant column and preventing the activation of a defective normal column, whereby the column redundancy method and apparatus minimizes the timing difference between a normal and redundant column paths and which minimizes the number of fuses required to be blown in repairing faulty columns addresses.

Abstract: This apparatus comprises a rigid half circular headclamp, three fixation pins to firmly secure the clamp to the patient's skull, a connector to firmly secure the clamp to a surgical table on which the patient rests, an articulated arm including clampable joints, secured to the headclamp in one of several possible positions and a double chuck secured to the distal end of the articulated arm. The double chuck has two ball collets arranged in side by side cavities in the chuck body, and two locking screws for each ball collet. A first locking screw releasably locks the ball collet in a selected orientation, a second separate locking screw releasably locks in an adjusted axial position an elongated instrument inserted through said collet. The first and second locking screws are actuated independently of each other. A computer guided probe and a large number of surgical instruments can be slidably inserted within the ball collets and locked in an adjusted axial position and in a selected orientation.

Abstract: In accordance with this invention there is provided a circuit for delaying a selected edge of an input signal for use in a deep sub-micron process semiconductor device, the circuit comprising an inverter element having an input and output node, a load element comprising resistive and capacitive (RC) elements a first transistor element, coupled to the RC load element and selectively operable to couple the RC element to the output node upon receipt of the selected edge of the input signal and for decoupling the RC element from the output node upon receipt of an opposite edge of the input signal, whereby a delay is introduced by the load element on the selected edge of the input signal with little negative effect on the opposite edge of the input signal.

Abstract: A display apparatus within elevator cabs or elevator waiting areas that facilitates the simultaneous display of advertising and general news information is described. Broadcast from a remote control center, advertising and general news information updates are transmitted to, and stored in a server located within a building and then forwarded to a display memory and subsequently displayed on a monitor according to a remotely modifiable program schedule. The display is updated such that it contains a copy of the latest broadcast schedule, as well as the advertisement and information programming, and automatically displays a days program according to the most current broadcast schedule. The display units as well as the building server are each individually addressable thus allowing groups of displays to be simultaneously updated from a remote centralized location with information such as news updates, customized advertising information and the like.

Abstract: A joint is formed between adjacent edges of a pair of weldable components by forming an undercut on one of the edges. The other edge abuts the undercut so that a portion of the one edge overlaps the other. The edges are laser welded by impinging a beam on the portion to melt the overlap.

Abstract: A regulator circuit is provided for use with cell plate voltage generators of memory cell capacitors and precharge bit lines voltage generators in semiconductor memories. The circuit employs a current source coupled to the charging reference voltage whose output is controlled by a level detector, which receives as input a reference level signal and the cell plate voltage. When the cell plate voltage drops below the reference level, the level detector triggers the current source, thereby recovering the cell plate voltage to the reference level. The level detector can be disabled through an input.

Abstract: A compact microwave oven is provided which has a top-opening, space-efficient housing. An optional container is also provided which is adapted to fit within the housing and to contain the foodstuff to be heated.

Abstract: A controller for controlling the pump unit of an oil well includes a sensor having a first and second probe for placement in the flow of oil from the well bore. Each of the probes contains a heater. A constant power source is selectively connected to one of the heaters. Each of the probes also include a linear RTD at each of their tips respectively for generating a signal indicative of the temperature measured at each of the first and second probes. A control unit receives signals from the RTD's and determines a flow rate therefrom. A pump control signal is generated in response to the flow rate, wherein pump control signal continuously varies a predetermined parameter of a pumping unit during operation of the pumping unit.

Abstract: This invention describes a column redundancy method and apparatus in a DRAM that minimizes the timing difference between a normal and redundant column paths and which minimizes the number of fuses required in repairing faulty columns. The invention discloses a DRAM having memory elements arranged in rows and columns, the memory elements being accessible by decoding a memory address applied thereto, normal column drivers for energizing appropriate memory columns in response to the decoder memory addresses received at an input thereof; redundant column drivers; and switch means for steering the decoded memory address onto one of either normal or redundant column driver paths. The invention further illustrates a fusing system which minimizes the capacitance of redundant select lines, thereby removing unnecessary delay in the redundant column path.

Abstract: The present invention provides a system and process for correlating points on a spatial body to corresponding points on a data-base body formed from pre-acquired images of the spatial body. The system and process involves matching the spatial points with the corresponding data-base points using relative positional information between the spatial points and the data-base points. Symmetric false matches are detected and discarded by fitting the spatial points and data-base points to a first and second closed body, respectively, and comparing the orientation of the spatial points and the data-base points projected onto the closed bodies.