Abstract: A high voltage generating circuit which provides a constant V.sub.PP output without any threshold voltage drop and which does not suffer from latch-up problems is described. Thus a voltage boosting circuit which provides for a boosted voltage V.sub.PP at an output node, from a supply voltage V.sub.DD, includes a precharge transistor element responsive to a precharge clock signal for transferring the supply voltage V.sub.DD to a boost node for precharging the boost node to the full supply voltage V.sub.DD. The circuit further includes a capacitive element connected between the boost node and a pump node, the capacitive element pumping the boost node in response to a pump voltage signal applied to the pump node; and a switching element connected between the boost node and the output node, for transferring charge from the capacitive element to the output node to provide the boosted voltage V.sub.PP. In particular the precharge transistor element is an PMOS transistor.

Abstract: This invention provides a data bit redundancy method and apparatus that permits the replacement of faulty bitlines on a data bit basis as opposed to a column address basis. This invention provides a semiconductor memory device having memory cells arranged in columns and rows. Normal local data lines are connected to a global data line via a first switch. A redundant memory data line is connected to the global data line via a second switch. A control generating first and second control signals are coupled to the respective first and second switches for operating the switch in response to a status of a fuse component, whereby when the fuse is intact the normal data lines are connected to the global data line and when the fuse is blown the redundant data lines are connected to the global data line, thus not requiring additional redundancy address decoding circuitry.

Abstract: This invention describes an addressing and data access method and apparatus which can make use of maximum sized, binary configured blocks of memory or macro cells. The binary sized blocks of memory may be used to implement a non-binary sized overall memory circuit. The apparatus as described makes efficient use of silicon area by combining an optimized number of memory blocks or macro cells having at least two data port per macro cell to implement a non-binary sized memory circuit.