Abstract: The invention relates to a method and an arrangement for controlling access to EEPROMs' and to a corresponding computer software product and a corresponding computer-readable storage medium, which can in particular be used to prevent the unauthorized manipulation of EEPROMs. Specifically, it is possible by using the invention to stop the unauthorized use of totally erased EEPROMs on smart-card controllers. EEPROM fuses that, depending on the application, comprise one or more bits, are used in the continuing course of operation of a controller, to permit or forbid security-related functions. Provision is made as part of the invention for EEPROM fuses to be used to permit writing to the EEPROM only if said fuse comprises a given combination of bits. Any manipulation of this fuse, such as by erasing the entire matrix for example or else by manipulating the booting process, then bars all further write accesses to the EEPROM.

Abstract: The invention relates to a radio communication system in which secondary stations (110) can request services from a primary station (100) using a random access channel employing a time division multiple access protocol, An access request comprises an access packet (200) having a predetermined maximum data capacity. If a secondary station requires to transmit an access request including more payload data (202,206) than can be accommodated in a single access packet the data is subdivided into a plurality of parts each of which is transmitted in a separate access packet. The primary station combines the data from the plurality of access packets (200) forming the access request, and issues an acknowledgement to the secondary station.

Abstract: The invention describes a display device for displaying information, comprising a display unit 1 with a plurality of columns C and rows R and a display driver 2. Further the invention describes a display driver 2 controlling a display unit 1 with storing means 3 for providing image information to the columns C of a display. The invention relates also to a terminal for mobile communication with a display device, having a display unit 1 and a display driver 2. To achieve a flexible multiplex rate of the display a control device 4 is arranged to switch off a definable number of rows R of the display depending on a state signal which contains the state information of the rows R. By this the multiplex rate is freely programmable, so in a partial mode (N/{overscore (P)}=0) the multiplex rate is reduced and by this the power consumption is reduced. Further it is possible to enable the rows or the groups of rows in a none consecutive order.

Abstract: A data carrier (1) comprises an integrated circuit (3), which integrated circuit (3) comprises a tolerance-defined main capacitor (35) which is connected to a coil (4) of the data carrier (1), and which integrated circuit (3) comprises at least one integrated additional capacitor (32) which is optionally connectable to the coil (4) of the data carrier (1) so that a parallel switching configuration of the main capacitor (35) with the at least one additional capacitor (32) is achievable. The optional parallel arrangement of the at least one additional capacitor (32) leads to a reduction of the tolerance range of the nominal capacitance of the main capacitor (35) when the effectively realized capacitance of the main capacitor (35) is reduced by a factor F and the at least one additional capacitor (32) has a fraction K of the nominal capacitance of the main capacitor (35).

Abstract: An identification transponder for transferring an identification code to a base station by varying an RF-signal transmitted by the base station in a rhythm which corresponds to the identification code. The identification transponder comprises an identification code generator, a rectifier; and a load transistor. The load transistor is arranged in such a manner that it performs two tasks: the task of rectifying the RF-signal to provide the DC supply voltage for the transponder, and the task of supplying a variable load to the rectifier to thereby vary the RF-signal transmitted by the base station.

Abstract: The invention relates to charge pump device and a display driver with a charge pump device. Further it relates to a display module with a display driver using a charge pump device and a telecom terminal having such a display module. To provide a device which needs a charge pump for generating a higher voltage as the supply voltage a charge pump device is proposed containing at least two stages (S), whereby a stage (S) comprises a switch (SWn) and a charge device (CSn) which are arranged to generate a voltage higher than the supply voltage (Vdd), whereby the stages (S) are arranged in serie and a required multiplication factor (MF) of the charge pump (CP) is adjustable by activating/deactivating a definable number of stages (S), whereby the switches (SWn) of each stage (Sn) are arranged in the same way.

Abstract: To provide an electric or electronic circuit arrangement as well as a method of detecting and/or identifying and/or recording at least an access violation, particularly at least a memory access violation, in a microcontroller provided particularly for a chip card or smart card, with which the source causing this access violation (referred to as break source) as well as the code address occurring upon this violation can be detected and/or identified and/or recorded when an access violation occurs during the program run, the circuit arrangement comprises at least a memory unit; at least an interface unit assigned to the memory unit; at least a processor unit connected to the memory unit particularly via the interface unit for executing instruction codes.

Abstract: An arrangement with a microprocessor, particularly a microprocessor for use in a chip card is described. The arrangement includes a microprocessor which is connected to at least a USB interfaces and an ISO interface for exchanging data signals. A selection unit within the microprocessor may be configured to select between the USB and ISO interfaces, and a switching unit within the microprocessor may be configured to subsequently switch between the USB and ISO interfaces by initiating an internal reset of the microprocessor.

Abstract: In a data carrier (1) having an electrical circuit (2), indication means (3) are implemented by means of the electrical circuit (2), which means are arranged so as to determine the occurrence of a change in a parameter influencing the data carrier (1) in relation to at least one threshold value, the at least one threshold value dividing a first parameter range from a second parameter range, and which means are arranged so as to give a permanent indication of the change during the time following the first occurrence of said change.

Abstract: A display device (1) provided with a digital thermometer on-chip (12), sensing the temperature of the supporting plate (3) of an electro-optical medium (4), for example, a liquid crystal display medium, while in a special embodiment, this digital temperature sensor and a column and/or row driver (5) are provided by means of thin film technology. In a preferred embodiment the temperature sensor and the column or row driver are integrated on one chip.

Abstract: A physical random number generator has a bi-stable latch that operates to latch a random number bit in response to a reception of a voltage oscillating signal. When a switching device is in a first operating state, the bi-stable latch is deactivated and an oscillator is activated to generate one or more unpredictable voltage oscillation signals, which may provoke the bi-stable latch into a metastable state upon an activation of the bi-stable latch. When the switching device is in a second operating state, the oscillator is deactivated and the bi-stable latch is activated to latch a random number bit as a function of the unpredictable voltage oscillation signals, the randomness of the random number bit being enhanced by any provoking of the bi-stable latch into the metastable state by the voltage oscillating signal(s).

Abstract: A method of checking the authenticity of a digital electric circuit arrangement is achieved in that a concatenation (6; 8, 9) of at least a few circuit-technical elements (10) of the electric circuit arrangement (1) is formed, which deviates from the normal, intended use of the circuit arrangement (1), in that a digital random value generated by the external device (2) and transferred to the electric circuit arrangement (1) is modified in said circuit arrangement by the concatenated elements (6; 8, 9) and transferred to the external device (2), in that the external device (2) compares the modified value with a check value assigned to the random value transferred to the electric circuit arrangement (1), and in that the authenticity of the electric circuit arrangement (1) is recognized only when the modified value and the check value correspond to each other.

Abstract: A transmitter for transmitting a high frequency transmit signal generates a low intermediate frequency quadrature signal, and up-converts the low intermediate frequency quadrature signal to the high frequency transmit signal. The frequency spectrum of the high frequency transmit signal has a transmit band and a sideband corresponding to the transmit band. The transmit band is confined to a total transmit band outside of which severe sideband filtering requirements.apply. Before up-converting, the transmitter provides that the sideband falls at a side of the transmit band such that the sideband falls within the total transmit band.

Abstract: A tag device is described for receiving, processing and/or transmitting data signals using an integrated electronic data-processing circuit formed in an essentially plane substrate body and at least two electrodes arranged on the plane substrate body, which electrodes are connected to the data-processing circuit in such a way that they are adapted to transmit and/or receive the data signals and/or electric power supply energy using offset currents produced via a quasi-static, electric alternating field. This tag device is very simple and inexpensive, and has a great reliability of operation. Furthermore, a system with such a tag device and a corresponding reading apparatus are described.

Abstract: A circuit arrangement comprising an input amplifier stage (31) with two inputs (36, 37) and an output (34) being connectable to an input (35) of an output amplifier stage (32). The circuit furthermore comprises a comparator (33) with a first input (41), a second input (42) and a comparator output (44), a feedback capacitor (43) connected to an offset tuning input (45) of the input amplifier stage (31), and a plurality of switches (S1, S2) that are controllable by switching signals (V1, V2) to allow the circuit to be switched from a first phase to a second phase. During the first phase (1), the output (34) and the input (35) are separated by a first one of the switches (S2) and the two inputs (36, 37) are connected via a second one of the switches (S1).

Abstract: Disclosed is a method that enables a smart card to exchange data with an apparatus, which is intended to supply the smart card with a permanent clock signal in a permanent mode of operation. The method according to the invention includes the steps of detecting, in the course of the permanent mode of operation, of an impending disappearance of the permanent clock signal, wherein the detecting step includes a comparison of the value of the amplitude of the permanent clock signal with a predetermined value; and substituting an auxiliary clock signal for the permanent clock signal. The invention enables the smart card to receive, after the disappearance of the permanent clock signal, a number of clock pulses which suffices for completing pending read/write operations.

Abstract: A communication station for contactless communication with suitably formed data carriers has an antenna configuration which has at least one antenna with at least one pole and at least one antenna with at least one essentially closed loop, and where the antenna with at least one pole is loosely electromagnetically coupled with the antenna with at least one essentially closed loop.

Abstract: A method of protecting a circuit arrangement for processing data, particularly a microprocessor, preferably a smart card controller, in which circuit arrangement, during and/or at the end of manufacturing this circuit arrangement and for the purpose of manufacturing control scan tests, a shift register chain is formed by combining memory cells of the circuit arrangement, preferably memory cells formed as flip-flops, in a predetermined configuration from these memory cells, by means of this shift register chain and/or another shift register chain formed in the circuit arrangement, arbitrary states are generated in the memory cells of the circuit arrangement and evaluated in a predetermined way for testing the functional capability of the memory cells of the circuit arrangement loaded with these states, after ending the manufacturing control scan test, the shift register chain is made unusable.

Abstract: Chip cards comprising a microprocessor and a memory are used for various applications. It is also desirable that such chip cards can be used for different applications. This requires a strict and reliable separation of the various user programs so that mutual accessing is not possible. This is achieved notably by subdivision into a system mode, in which all access rights are free, and a user mode which is adjusted by way of a given bit in the program status word. This mode bit controls inter alia a separation in the bus for the special function registers so that given registers are not accessible in the user mode. These registers may contain information enabling the access to given memory sections only, so that this access cannot be modified in the user mode.

Abstract: In a node of a data communication system with a number of nodes, in which data communication system isochronous and asynchronous data is exchanged through a serial data bus structure, multiple link layer interface circuits are coupled to a single physical layer interface circuit. The physical layer interface circuit has an external port through which the physical layer interface circuit is connected to the serial bus structure. The physical layer interface circuit is coupled to the link layer interface circuits through bi-directional switches. A logic circuit controls the bi-directional switches and, in dependence of configuration information stored in configuration registers of the link layer interface circuits and its own programming, the logic circuit controls routing of isochronous and asynchronous data streams from the link layer interface circuits to the physical layer interface circuit, and from the physical layer interface circuit to the link layer interface circuits.