Abstract: The invention relates to a circuit for the detection of short voltage glitches in a supply voltage Vsup (glitch detector). According to the circuit the two inputs (VN, VP) of a comparator (C) are connected to a voltage divider (R1, R2, R3). In case of a short voltage glitch the connection of the first input (VN) of the comparator (C) to the voltage divider is interrupted via a first transistor (N1), so that this input is fixed at the previous voltage level, while the other input (VP) changes in accordance with the voltage glitch. If the change is strong enough, there is a polarity reversal at the input of the comparator (C) and thus a flipping of the output signal (OUT) which shows the detection of a voltage glitch.

Abstract: A transponder (1) and an integrated circuit (4) have at least one signal channel (5, 6, 7), each signal channel (5, 6, 7) having at least two signal processing stages (25, 26, 27, 28, 29, 30, 31) and at least one signal processing stage (26, 27, 29) configured such as to be activatable and deactivatable, while an associated bypass branch (32, 33, 34), which is also activatable and deactivatable, is provided for each activatable and deactivatable signal processing stage (26, 27, 29), and a microcomputer (36) and a control register (37) controllable by the microcomputer, (36) are provided, by means of which each activatable and deactivatable signal processing stage (26, 27, 29) and the associated bypass branch (32, 33, 34) are activatable and deactivatable in counterphase.

Abstract: An arrangement for a passive keyless entry system is disclosed, comprising a base station and a portable data carrier, wherein the data carrier and the base station are configured to determine authorized access of the base station, wherein first and second position information of the relative position of the data carrier with respect to the antenna coils and UHF receiver stages of the base station is gained from measurements of the low-frequency, magnetic alternating fields transmitted by LF transmitter stages of the base station to the data carrier, and the UHF signal transmitted by a UHF transmitter stage of the data carrier to the base station, wherein a signal representing authorized access is generated by the base station when both position information components differ by less than a predetermined extent.

Abstract: A description is given of a circuit arrangement for electronic data processing which includes a writeable memory for storing data to be protected against unauthorized access, a read-only memory for storing individualizing data, a control unit for generating given control signals in dependence on a reset signal sequence to be executed by the control unit during operation of the circuit arrangement, a scrambling pattern generator for generating scrambling pattern signals by combining at least a part of the individualizing data from the read-only memory with the control signals during the execution of the reset signal sequence and for subsequently outputting these scrambling pattern signals until the execution of a next reset sequence, and a scrambling logic unit for the scrambling of address and/or data signals of the data to be stored in the writeable memory in conformity with the scrambling pattern signals supplied by the scrambling pattern generator upon storage of this data, and for the corresponding descra

Abstract: The invention relates to a circuit arrangement for pulse generation, having a capacitor, to which a charging current and a discharging current may be supplied in succession. To generate the charging current and the discharging current, there are provided a current source, a first current mirror circuit and a second current mirror circuit complementary to the first current mirror circuit. The current mirror circuits each comprise a plurality of output transistors, which each constitute an output stage for the charging and discharging current, which is connected to a regulator, and for a circuit for controlling the tail current of a differential amplifier forming the regulator. A current output of the differential amplifier is connected to the output of the second current mirror circuit.

Abstract: A set of class AB output stages are cascaded to provide a class AB device circuit which utilizes relatively small transistors, low power, and virtually eliminates crossover distortion. The input may be powered by a voltage or a current source.

Abstract: A module (2) for a data carrier (1) includes an integrated circuit device (9) and transmission means (10), and the module (2) can be tested with the aid of test means (19) during a test operation, which test means (19) can generate a test-result signal (TRS2, TRS3) in dependence on a test result thus determined, indication means (22), which are electrically switchable to a given indication mode (“1”, “0”) in dependence on the test-result signal (TRS2, TRS3), which indication means (22) are advantageously arranged directly on the module (2).

Abstract: A circuit arrangement (100) for controlling a first terminal and a second terminal of a preferably contactless integrated circuit, particularly for testing a CMOS circuit, tests a multitude of intergrated circuits simultaneously while using a low-cost structure. The circuit arrangement permits a simple write/read unit assigned to the integrated circuit, and enables the simultaneous testing of a multitude of integrated circuits using a low-cost structure.

Abstract: A module (1) for a data carrier (3) for performing of operations with contacts and operations without contacts comprising an integrated component (4) with component connections (A1, A2, A3, A4, A5, A7, A8) and having a contact field (5) accessible to counter contacts with module connecting contacts (C1, C2, C3, C4, C5, C6, C7, C8), with each component connection (A1, A2, A3, A5, A7) used for operations with contacts being in an electrically conductive connection with a module connecting contact (C1, C2, C3, C5, C7) of the contact field (5) and each component connection (A4, A8) used for operations without contacts also being in an electrically conductive connection with a module connecting contact (C4, C8) of the contact field (5).

Abstract: A data carrier (1) for contactless communication with a communication station has a substrate (2) and a communication resonant circuit (3) connected to the substrate (2) and consisting of a communication coil (4) and of a capacitor configuration (6) and having a resonant frequency (fR) which should have a nominal value, changing unit (9) for changing the resonant frequency (fR) being provided, which changing unit enable the resonant frequency (fR) to be changed from an initial value both to higher frequency values and to lower frequency values.

Abstract: In order to preclude unauthorized access to a memory, for example after testing, two EEPROM cells are programmed and their outputs are subjected to a logic operation, the result being stored in a memory element and being evaluated. The cells are arranged in such a manner that they are programmed together in anti-parallel. A well-defined initial condition before a test is established by changing the control gate voltage, which causes both cells to be set to an initial state with similar output signals. The initial state is stored in the storage element and is evaluated. It is not until the initial condition has been established that the EEPROM cells are programmed and the correct programming is tested. Locking is effected by means of a single programming pulse and is irreversible.

Abstract: Home networks of different software architectures are integrated with each other. References to software representations of devices and services on a first one of the networks are automatically created. The references are semantically sufficient to enable automatic creation of at least partly functionally equivalent software representations for a second one of the networks so as to make the devices and services of the first network accessible from the second network.

Abstract: In a radio communication system having a primary station and a plurality of secondary stations, the power of uplink and downlink channels between the primary station and a secondary station is controlled in a closed loop manner by each station transmitting power control commands to the other station. In response to these commands the receiving station adjusts its output power in steps. By combining a plurality of received power control commands before adjusting its output power the receiving station may emulate the ability to use a smaller power control step size than its minimum, thereby improving performance under certain channel conditions. In one embodiment when the required power control step size is less than the minimum step size of a particular station, that station processes a group of power control commands to determine whether to adjust its output power by its minimum step size. In an alternative embodiment the power control step size is fixed when the combining algorithm is used.

Abstract: The operability and scaleability of electronic circuits is improved using a circuit arrangement that is modular, scaleable, straightforward to implement and allows for simple and safe physical design implementation. According to one example embodiment of the present invention, a reset method and system are used to effect a reset at several peripheral devices that may employ similar and/or different reset strategies. A reset module is coupled to a clock module having an external clock reference and to each of the peripheral devices. Operationally, the clock module provides a functional clock signal to each of the peripheral devices at one of a plurality of first frequencies. The reset module generates an internal reset signal in response to a system reset signal. In response to an internal reset signal, the clock module drives a common reset clock signal, having a reset clock frequency, to each of the peripheral devices via clock outputs at the clock module.

Abstract: A circuit arrangement and method reduce the number of interconnects required for a digital signal processor by utilizing a shared bus to interconnect the digital signal processor to both a program memory and at least one external device. An instruction cache is utilized to cache selected instructions from a DSP program such that, whenever a cached copy of a DSP program instruction is available in the instruction cache, the cached copy can be fetched from the instruction cache instead of the program memory, thereby freeing the shared bus for performing an access to the external device. Caching of instructions and subsequent freeing of the shared bus for external device access may be conditioned on detection of a loop, whereby instructions from the loop are cached in the instruction cache and fetched during subsequent passes through the loop.

Abstract: A wireless system comprises a number of wireless stations for communication with each other through short-range wireless links. In a multiple link data object conveying method, in a data conveying session, a first short-range wireless link is set up between a first and a second wireless station of the wireless system. Upon setting up of the first short-range wireless link, first and second personal identification codes are respectively entered in the first and second wireless stations. Thereafter, a data connection through the first wireless link is only set up if the first and second entered personal identification codes are the same. If the data connection is set up the first personal identification code is stored for later use in the session, and the data object is conveyed through the first wireless link. Then, while using the stored first personal identification code, at least a subsequent short-range wireless link is set up from the first wireless station to a third wireless station.

Abstract: Each coil of a transformer is partitioned into two or more parallel segments. The multiple segments of each coil are interleaved with each other to form a coplanar interleaved transformer that has a greater coupling efficiency than a non-segmented coplanar interleaved transformer. In a preferred embodiment, the multiple segments are of reduced width, so that the interleaved coils consume substantially the same area as the non-segmented coplanar interleaved transformer, thereby maintaining the same inductance as the non-segmented transformer. To provide for maximum efficiency, each segment of each coil is embodied so as to have substantially equal length as each other segment of the coil.

Abstract: A method and apparatus are disclosed for calculating and validating the differential time between the broadcasting of an event and the time at which a user responds. The event may include, for example, the announcement of an auction or a contest on a television program. The differential time for each end-user response is calculated by each end-user device. The user response can be reported back to the service provider in a secure and reliable off-line or real-time manner. Each end-user device can include a secure time-keeping device having a secure clock/calendar feature for calculating the differential time between presentation of the event and the user response. A user is prevented from recording a particular event and thereafter replaying the recorded event and responding to the replayed event, to thereby alter the effective response time. Local and global presentation time information are compared to ensure that each user responds to the initial, real-time event and not a replay.

Abstract: A frequency generating circuit comprises a first, fine PLL frequency synthesiser circuit (FS2) which consumes a low current and is slow to settle, a second, coarse PLL frequency synthesiser circuit (FS1) which consumes a high current and is fast to settle, and a signal combining circuit (36) for additively combining the outputs of the first and second frequency synthesiser circuits to provide a final output frequency. The first frequency synthesiser circuit is energised sufficiently in advance of the second frequency synthesiser circuit that both achieve lock substantially simultaneously. The overall current consumed is less than would be consumed if a single PLL frequency synthesiser is used to generate the final frequency.

Abstract: A magnetic head reader circuit comprises a gain stage that is configured to effect multiple functions. In a preferred embodiment, the gain stage is a single stage circuit that includes programmable gain, programmable bandwidth and high-frequency boost, and squelch control. The single stage circuit also includes a folded cascode current drive that provides an increased dynamic range of the gain stage. To provide a low DC offset, the reader also includes an integrator that is operated in closed loop to appropriately attenuate the currents from the cascode current drive. By employing a multi-function single stage reader, a substantial reduction in circuit area, and a substantial increase in bandwidth, is achieved.