Abstract: A transistor comprising a plurality of active semiconductor layers on a substrate, with source and drain electrodes in contact with the semiconductor layers. A gate is formed between the source and drain electrodes and on the plurality of semiconductor layers. A plurality of field plates are arranged over the semiconductor layers, each of which extends from the edge of the gate toward the drain electrode, and each of which is isolated from said semiconductor layers and from the others of the field plates. The topmost of the field plates is electrically connected to the source electrode and the others of the field plates are electrically connected to the gate or the source electrode.

Abstract: A common mode rejection calibration scheme for use with a difference amplifier having an associated signal path. A signal is generated which varies with the common mode voltage of the differential input voltage applied to the amplifier. This signal is scaled and coupled into the signal path such that the scaled signal reduces the common-mode error that would otherwise be present in the difference amplifier's output.

Abstract: Methods and systems for coating of semiconductor devices using droplets of wavelength conversion or phosphor particles in a liquid medium. A plurality of nozzles delivers a controlled amount of the matrix material to the surface of the semiconductor device, with each of said nozzles having an opening for the matrix material to pass. The opening has a diameter wherein the diameter of the phosphor particles is less than or approximately equal to one half the diameter of the opening. The phosphor particles are also substantially spherical or rounded. The nozzles are typically arranged on a print head that utilizes jet printing techniques to cover the semiconductor device with a layer of the matrix material. The methods and systems are particularly applicable to covering LEDs with a layer of phosphor materials.

Abstract: Semiconductor light emitting devices are fabricated by placing a suspension including phosphor particles suspended in solvent on at least a portion of a light emitting surface of a semiconductor light emitting element, and evaporating at least some of the solvent to cause the phosphor particles to deposit on at least a portion of the light emitting surface. A coating including phosphor particles is thereby formed on at least a portion of the light emitting surface. Particles other than phosphor also may be coated and solutions wherein particles are dissolved in solvent also may be used.

Abstract: A current-mode instrumentation amplifier (IA) error reduction circuit and method employs a current-mode IA topology and an auto-zero circuit. The IA receives a differential voltage (VINP?VINN) and produces differential DC currents (IDC1, IDC2) in response, which are summed to produce the amplifier's output current. Ideally, when VINP=VINN, IDC1 and IDC2 will be equal; however, due to mismatches an error component Ierror will be present such that IDC1=IDC2±Ierror. The auto-zero circuit is employed to reduce the magnitude of Ierror. In operation, in an ‘auto-zero mode’, VINP and VINN are connected together and the auto-zero circuit operates to make IDC1=IDC2; a voltage needed to effect this is stored. Then, in ‘normal mode’, VINP and VINN are disconnected from each other and the IA is placed in the signal path, with the stored voltage acting to keep the magnitude of Ierror low.

Abstract: A mask layer is applied to a surface of a semiconductor structure or a seed layer deposited on the surface. The mask layer has a submicron width opening with a high aspect ratio that exposes a portion of the surface or seed layer. Conductive material is conformed to the opening, for example by plating, to form a first contact on the surface or seed layer. The mask and the top layer of the semiconductor structure, except for the portion under the first contact, are removed to expose a second layer of the semiconductor structure. An insulating layer is formed along the sidewalls of the first contact and the top layer of the semiconductor structure beneath the first contact. A mask is then applied to the second layer and a second contact is formed by selectively depositing metal only on the portion of the second layer exposed by the opening.

Abstract: A thermal barrier apparatus includes a lens cell with a vacuum chamber, the lens cell having opposing lenses, and a one-way gas valve coupled to the lens cell to allow venting of the vacuum chamber in response to thermal expansion of gas in the vacuum chamber.

Abstract: A duty cycle management system and method for use in a wireless device having a transmitter which transmits packets in the form of individual packets and/or packet bursts. A controller in combination with an instruction set limits the number of packets transmitted during each time period defined by one time window or adjacent time windows, on a sliding basis, so as to control the duty cycle of transmissions during successive adjacent time windows based on the transmitter's output power, to produce that average power output. The transmission of packets is thereby delayed as needed to establish sufficient idle period(s) during one time window or adjacent time windows to apply whatever duty cycle is needed to produce that average power output level limit for the transmitter.

Abstract: An IC current reference includes a reference voltage Vref, a current mirror, and a transistor connected between the mirror input and a first I/O pin and which is driven by Vref. A resistor external to the IC and having a resistance R1 is coupled to the first I/O pin such that it conducts a current Iref which is proportional to Vref/R1; use of a low TC/VC resistor enables Iref to be an accurate and stable reference current. The current mirror provides currents which are proportional to Iref, at least one of which is provided at a second I/O pin for use external to the IC. One primary application of the reference current is as part of a regulation circuit for a negative supply voltage channel, which can be implemented with the same number of external components and I/O pins as previous designs, while providing superior performance.

Abstract: An in-grade light fixture comprises a light fixture housing arranged to be buried substantially below grade level. The light fixture housing has a light opening substantially at grade level and an optical chamber having a light source arranged within the optical chamber and the optical chamber arranged within the housing with light from the light source passing through the light opening. The fixture further comprises a plurality of housing openings and one or more enclosures, each of which is removably mounted to a respective one of the housing openings. The enclosures accept external power and generate power to energize the light source causing it to emit light. The optical chamber can also comprise an anti-condensation valve and an air passageway between the optical chamber and one of the enclosures form a vacuum in the optical chamber and vacuum during operation.

Abstract: An amplifier topology includes an input stage comprising a differential pair which conducts respective output currents in response to a differential input signal. Bias current sources provide the pair's tail current and respective bias currents for the input stage in response to a drive voltage. After flowing through the input stage, most or all of the input stage bias currents are summed at a summing node, the summed currents being a current Isum. The input stage also has a feedback loop which includes a bias generator circuit arranged to receive Isum, and to provide the drive voltage to the bias current sources such that Isum is maintained approximately constant. By so doing, the output impedance of the bias current sources is effectively increased, which serves to improve the amplifier's CMR and PSR characteristics.

Abstract: A HEMT comprising a plurality of active semiconductor layers formed on a substrate. Source electrode, drain electrode, and gate are formed in electrical contact with the plurality of active layers. A spacer layer is formed on at least a portion of a surface of said plurality of active layers and covering the gate. A field plate is formed on the spacer layer and electrically connected to the source electrode, wherein the field plate reduces the peak operating electric field in the HEMT.

Abstract: An electric strike comprising a housing and a keeper pivotally mounted to said housing. A solenoid is arranged internal to the housing and movable between fail-safe and fail-secure positions. A two position mode control slot is included in the housing and a mode control screw is included in the mode control slot. The screw is capable of being tightened in each of the two positions in the control slot. The screw is changeable between the two of the positions without removal of the screw. The solenoid is in the fail-safe position when the screw is in one of the two positions and in the fail-secure position when the screw is in the other of the two positions.

Abstract: Embodiments of the present invention are directed to a process for forming small diameter vias at low temperatures. In preferred embodiments, through-substrate vias are fabricated by forming a through-substrate via; and depositing conductive material into the via by means of a flowing solution plating technique, wherein the conductive material releases a gas that pushes the conductive material through the via to facilitate plating the via with the conductive material. In preferred embodiments, the fabrication of the substrate is conducted at low temperatures.

Abstract: The surface morphology of an LED light emitting surface is changed by applying a reactive ion etch (RIE) process to the light emitting surface. Etched features, such as truncated pyramids, may be formed on the emitting surface, prior to the RIE process, by cutting into the surface using a saw blade or a masked etching technique. Sidewall cuts may also be made in the emitting surface prior to the RIE process. A light absorbing damaged layer of material associated with saw cutting is removed by the RIE process. The surface morphology created by the RIE process may be emulated using different, various combinations of non-RIE processes such as grit sanding and deposition of a roughened layer of material or particles followed by dry etching.

Abstract: New methods of operating surface reactors, and such reactors, particularly spinning disk reactors, require that a first reactant is fed to a reactor surface (20) and forms a thin radially outward moving film (60) thereon in a reaction passage (42) formed between the reaction surface (20) and a parallel, closely spaced (less than 1 mm) retaining surface (40). The passage thickness is precisely controllable and the surfaces (20, 40) move relative to one another so that strong shear is applied to the material between them. A second reactant is fed to the surface (20) as a second thin film (65) that as it enters the first film (60), preferably perpendicularly, it is immediately merged therewith along a correspondingly very narrow interaction line (66) by the shear at a rate such as to break up molecular clusters in the films, so that their molecules can aggressively and completely interact by forced interdiffusion.

Abstract: A digital controller for use with a full-bridge power converter which includes an isolation transformer that conducts first and second currents of opposite polarity during respective power-transfer phases. A current transformer senses the currents, and a non-zero current Iin is generated when either of the first or second currents is >0. The controller includes a sigma-delta modulator arranged to integrate a current applied to its input and to modulate the integrated signal to a bitstream. Iin is integrated by a first integrator and the bitstream is decimated to a digital word by a first decimation filter during the first power-transfer phase, and is integrated by a second integrator and decimated with a second decimation filter during the second phase. The difference between the digital values is used to adjust the pulses that operate the full-bridge switches as necessary to reduce any imbalance between the first and second currents.

Abstract: Amplifier embodiments are provided that are well suited for systems which require high signal gains and high transient currents that can drive various loads (e.g., capacitive loads). At least one amplifier embodiment is realized with a cascoded complementary differential input stage, a complementary differential output stage, and a bias controller. The output stage includes lower and upper differential pairs of transistors that respectively have lower and upper coupled back gates and the bias controller is configured to provide bias voltages for the lower and upper coupled back gates.