Patents Represented by Attorney Koppel, Patrick, Heybl & Dawson
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Patent number: 7521726Abstract: A light emitting diode (LED) array with beam directors outputting a high-intensity collimated beam. The LED array is constructed from a substrate component on which the LEDs and necessary electronics are disposed and a director attachment having a plurality of beam directors. The beam directors have a unique structure that is designed to shape the light beam into a collimated form. The LEDs are arranged in a pattern on the substrate, and the beam directors are arranged within the director attachment to coincide with the LEDs. The substrate and the director attachment may be manufactured and processed as separate components; they are then affixed together for operation.Type: GrantFiled: May 4, 2006Date of Patent: April 21, 2009Assignee: Illinois Tool Works Inc.Inventors: Russell A. Dahl, Joseph W. Partlow, Stephen Proulx
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Patent number: 7520628Abstract: A high-power LED lamp comprises a cylindrical housing having a cavity and an open end with the housing made of a heat conductive material. One or more high power LEDs are mounted within the cavity such that at least some of the light from the LEDs is directed out the open end of the housing. An encapsulating material fills the cavity and surrounds the LEDs with the encapsulating material providing a waterproof covering over the LEDs and at least partially transmitting light from the LEDs out the opening. Heat from the LEDs conducts away from the LEDs and through the encapsulating material and the housing to dissipate in the ambient around the lamp.Type: GrantFiled: October 22, 2004Date of Patent: April 21, 2009Assignee: SloanLED, Inc.Inventors: Thomas C. Sloan, Bruce Quaal
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Patent number: 7519477Abstract: A method for determining impedance coefficients of a seismic trace comprises determining reflection coefficients of the seismic trace, for example using a sparse spike inversion, integrating the reflection coefficients with respect to time to obtain impedance coefficients, and filtering the impedance coefficients by applying a low-cut window filter. The window size and/or shape may be defined by a variable parameter which may be either specified by a user or optimized on the basis of a lateral variability parameter calculated for different values of the window parameter.Type: GrantFiled: October 20, 2006Date of Patent: April 14, 2009Assignee: BHP Billiton Innovation Pty Ltd.Inventors: Michael Edwin Glinsky, Jerome Kalifa, Stephane Mallat
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Patent number: 7514888Abstract: A method and system for providing sensorless brushless DC motor control using predictive switch timing requires connecting a stator coil in a bridge configuration, applying a positive excitation voltage across the coil for a predetermined time period, deactivating the excitation voltage, and monitoring the voltage (VEMF) generated due to electro-motive force (EMF) across the coil. The polarity of VEMF changes when the rotor has moved a known distance—typically 90°. After detecting a polarity change, a negative excitation voltage is applied across the coil, deactivated, and VEMF monitored to detect a polarity change. This sequence is repeated to maintain the rotation of the rotor. The motor is preferably set into motion using a start-up routine, which also determines the predetermined time period used during steady-state operation.Type: GrantFiled: November 1, 2006Date of Patent: April 7, 2009Assignee: Analog Devices, Inc.Inventors: Anthonius Bakker, Navdeep Singh Dhanjal
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Patent number: 7515231Abstract: An anisotropic cross-linked PVA alignment layer for aligning nematic polymeric liquid crystal compensator films, which also provides an out-of-plane retardation. The cross-linked PVA alignment layer, when applied in sufficient thickness functions as both a negative uniaxial C-plate and causes alignment of the nematic liquid crystal molecules. The combination of the retardation provided by the alignment layer and the compensator film deposited on it provides a significant improvement in the contrast and color stability of liquid crystal displays (LCDs) at large viewing angles in which they are used.Type: GrantFiled: September 30, 2005Date of Patent: April 7, 2009Assignee: Teledyne Scientific & Imaging, LLCInventors: Leonard G. Hale, Young J. Chung, William J. Gunning, III
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Patent number: 7516016Abstract: A method for improving prediction of the viability of potential petroleum reservoirs, utilises a rock physics model appropriate for porous media, in which some of the solid material is “floating” or not involved in load support, and predicts permeability on the basis of compressional wave velocity vs. density trends, which may be determined by wireline log. In a further aspect, by introducing the concept of the capture fraction of smaller grains, another constraint is added to the model, which enables an improved estimate of permeability to be determined on the basis of seismic reflectivity measurements alone.Type: GrantFiled: June 9, 2006Date of Patent: April 7, 2009Inventors: David C. DeMartini, Michael Edwin Glinsky
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Patent number: 7511939Abstract: A layered capacitor structure comprises two or more semiconductor/dielectric plates formed above an insulating surface which provides mechanical support, with the plates arranged in a vertical stack on the insulating surface. An insulating layer is on each plate, patterned and etched to provide an opening which allows the top of one plate to be in physical and electrical contact with the bottom of the subsequent plate. Contact openings are provided through the insulating layers, each of which provides access to a respective semiconductor layer and is insulated from any other semiconductor/dielectric plate. Electrical contacts through the contact openings provide electrical connections to respective semiconductor layers. The present structure can include as many stacked layers as needed to provide a desired total capacitance or range of capacitances.Type: GrantFiled: August 24, 2007Date of Patent: March 31, 2009Assignee: Analog Devices, Inc.Inventors: Craig Wilson, Michael Dunbar, Derek Bowers
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Patent number: 7511563Abstract: A ripple current reduction circuit includes a supply node coupled to the output of a high ripple voltage source such as a charge pump. A first current mirror is referred to the supply node and mirrors a current I1 to a second node, the mirrored current (I3) including a ripple current induced by the ripple voltage. A second current mirror is referred to the second node and mirrors a current I2 to an output node, which provides a current ILOAD to a load. The mirrors are sized such that the current provided at the second node is greater than the current required by the second mirror to provide ILOAD. The excess current, at least a portion of which includes a ripple component induced by the ripple voltage, is shunted to ground. As such, the magnitude of the ripple component in ILOAD is less than that present in I3.Type: GrantFiled: August 23, 2007Date of Patent: March 31, 2009Assignee: Analog Devices, Inc.Inventors: Thomas L. Botker, Benjamin A. Douts
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Patent number: 7501669Abstract: A transistor structure comprising an active semiconductor layer with metal source and drain contacts formed in electrical contact with the active layer. A gate contact is formed between the source and drain contacts for modulating electric fields within the active layer. A spacer layer is formed above the active layer and a conductive field plate formed above the spacer layer, extending a distance Lf from the edge of the gate contact toward the drain contact. The field plate is electrically connected to the gate contact.Type: GrantFiled: August 31, 2004Date of Patent: March 10, 2009Assignee: Cree, Inc.Inventors: Primit Parikh, Yifeng Wu
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Patent number: 7495426Abstract: A temperature setpoint circuit comprises bipolar transistors Q1 and Q2 which receive currents I1 and I2 at their respective collectors and are operated at unequal current densities, with a resistance R1 connected between their bases such that the difference in their base-emitter voltages (?Vbe) appears across R1. An additional PTAT current I3 is maintained in a constant ratio to I1 and I2 and provided to the collector of Q2 while Q2 is off, and is not provided while Q2 is on. The circuit is arranged such that Q2 is turned on and conducts a current equal to Ia when: ?Vbe=(kT/q)ln(NI1/Ia), where Ia=I2+I3, the temperature T at which ?Vbe=(kT/q)ln(NI1/Ia) being the circuit's setpoint temperature, such that the switching of current I3 provides hysteresis for the setpoint temperature which is approximately constant over temperature.Type: GrantFiled: March 6, 2006Date of Patent: February 24, 2009Assignee: Analog Devices, Inc.Inventors: Chau C. Tran, A. Paul Brokaw
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Patent number: 7491920Abstract: A cost-effective FPA includes a plurality of detectors per pixel, wherein radiation is directed by a microlens array into respective focal regions that are covered by the union of the detectors' collections regions within each pixel and any defective detectors are de-selected in the ROIC. The operability of each pixel is evaluated, and a map generated specifying detector de-selection for each pixel. This map is read into memory in the ROIC to de-select bad detectors. Bad detectors are preferably allowed to float to a photovoltage and re-emit some of their accumulated photo charge to neighboring detectors to improve collection efficiency. The radiation levels are preferably read out on a pixel-by-pixel basis. Accordingly, the signals from the selected detectors are combined within each pixel.Type: GrantFiled: February 2, 2006Date of Patent: February 17, 2009Assignee: Teledyne Scientific & Imaging, LLCInventors: Donald L. Lee, William E. Tennant
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Patent number: 7479799Abstract: An output buffer with a switchable output impedance designed for driving a terminated signal line. The buffer includes a drive circuit, and a means for switching the output impedance of the drive circuit between a first, relatively low output impedance when the output buffer is operated in a ‘normal’ mode, and a second output impedance which is greater than the first output impedance when operated in a ‘standby’ mode. By increasing the drive circuit's output impedance while in ‘standby’ mode, power dissipation due to the termination resistor is reduced. When used in a memory system, additional power savings may be realized by arranging the buffer such that the increased impedance in ‘standby’ mode shifts the signal line voltage so as to avoid the voltage range over which a line receiver's power consumption is greatest.Type: GrantFiled: March 14, 2006Date of Patent: January 20, 2009Assignee: Inphi CorporationInventors: Gopal Raghavan, Dhruv Jain
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Patent number: 7478776Abstract: A retracting tether apparatus is disclosed comprising a retractor housing having a locking post on its outside surface. The apparatus also includes an attachment mechanism, such as a belt clip, for attaching to a body and a retaining section, the attachment mechanism being integral to the retaining section. The retaining section has a retaining section hole sized to mate with the locking post and the locking post has a mechanism for holding the post in the retaining section hole. The inside surface of the retaining section hole rides on an outside surface of the locking post to provide for smooth rotation of the retractor housing in relation to the retaining section.Type: GrantFiled: November 10, 2005Date of Patent: January 20, 2009Assignee: Hammerhead Industries, Inc.Inventors: John A. Salentine, Kenneth S. Collin, Jr.
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Patent number: 7476956Abstract: New Group III based diodes are disclosed having a low on state voltage (Vf) and structures to keep reverse current (Irev) relatively low. One embodiment of the invention is Schottky barrier diode made from the GaN material system in which the Fermi level (or surface potential) of is not pinned. The barrier potential at the metal-to-semiconductor junction varies depending on the type of metal used and using particular metals lowers the diode's Schottky barrier potential and results in a Vf in the range of 0.1-0.3V. In another embodiment a trench structure is formed on the Schottky diodes semiconductor material to reduce reverse leakage current. and comprises a number of parallel, equally spaced trenches with mesa regions between adjacent trenches. A third embodiment of the invention provides a GaN tunnel diode with a low Vf resulting from the tunneling of electrons through the barrier potential, instead of over it. This embodiment can also have a trench structure to reduce reverse leakage current.Type: GrantFiled: May 20, 2003Date of Patent: January 13, 2009Assignee: Cree, Inc.Inventors: Primit Parikh, Umesh Mishra
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Patent number: 7470968Abstract: A passive matching network is connected to an input/output line for an automatic test equipment drive channel to compensate for capacitances associated with a receiver circuit connected to the line, and also an optional current-mode driver circuit. The matching circuit preferably comprises a T-coil circuit that can include a bridging capacitor; separate T-coil circuits can be provided to separately compensate for receiver circuit and current-mode driver circuit capacitances. The driver and receiver circuits can be implemented on a common layer of an integrated circuit, with the T-coil windings implemented in a separate layer of the same integrated circuit that is spaced from the common layer by at least one dielectric layer.Type: GrantFiled: January 4, 2006Date of Patent: December 30, 2008Assignee: Analog Devices, Inc.Inventors: Douglas W. Babcock, Robert A. Duris, Bruce Hecht
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Patent number: 7462160Abstract: An orthotic device includes a composite strut, a footplate removeably attached to a lower end of the strut, an upper tibial cuff removeably attached to an upper end of the strut and a lower tibial cuff removeably attached to a central portion of said strut. The footplate, upper tibial cuff and lower tibial cuff are formed of a composite material, preferably a carbon fiber composite. Each of the footplate, upper tibial cuff and lower tibial cuff include a support structure molded into the component with threaded holes therein. The upper and lower end of the strut may also include mounting holes therein for bolting the upper tibial cuff and footplate thereto. Mounting structure may also include mounting plates positioned on the rear surface of the strut and one or more tapered wedges mounted between the mounting structure on a rear of the strut, said tapered wedges allowing an angled orientation of the footplate and cuffs in relationship to the surface of the strut to which it is attached.Type: GrantFiled: July 27, 2005Date of Patent: December 9, 2008Inventors: Ralph W. Nobbe, Erwin A. Nobbe
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Patent number: 7461970Abstract: A mixing apparatus comprises first and second opposing mixing members rotatable relative to one another about an axis and which have facing surfaces which extend away from the axis and which define a mixing chamber therebetween. Means are provided for rotating at least one of the mixing members to provide relative rotation between the first and second mixing members in a first rotational direction. An array of mixing formations on at least one of said surfaces interact to mix material within the mixing chamber and are configured to propel material within the mixing chamber towards the axis. The number of mixing formations on at least one of the surfaces increases with radial distance from the axis.Type: GrantFiled: December 9, 2002Date of Patent: December 9, 2008Assignee: Watson Brown HSM LtdInventor: Christopher Brown
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Patent number: 7456853Abstract: Display structures and methods are provided that introduce redundancy and use this redundancy with different mapping rules on different interleaved display lines to visually diffuse display artifacts. The artifacts are typically produced by errors in the transmission and recovery of analog display signals that subsequently drive digital displays. This visual diffusion substantially reduces the display artifacts and, because these visual improvements require only one element (an ADC) in the display system to be configured at a higher resolution, the visual advantageous are realized with relatively low cost.Type: GrantFiled: October 22, 2004Date of Patent: November 25, 2008Assignee: Analog Devices, Inc.Inventor: Willard Kraig Bucklen
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Patent number: 7448768Abstract: An elongated perimeter light comprising a linear array of light sources (LEDs) that are electrically illuminated. The array of light sources is disposed within an elongated transparent tube, with the tube transmitting and dispersing the light from the array giving the appearance that said array of light sources is a continuous light source. The array of light sources is capable of being cut at intervals down its length to shorten it. The light sources that remain in the array continue to emit light and the tube can be cut to match the length of said array. Systems for lighting structural features comprising a plurality of elongated perimeter lights electrically coupled in a daisy chain with the electrical power at each of the perimeter lights being transmitted to the successive light. Each of the perimeter lights can be cut at intervals down its length.Type: GrantFiled: April 5, 2005Date of Patent: November 11, 2008Assignee: SloanLED, Inc.Inventors: Thomas C. Sloan, James J. Sloan
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Patent number: 7450539Abstract: A communication system includes a multi-channel signal regulation system that limits an aggregate signal in response to an indication that the aggregate signal exceeds a threshold value. The aggregate signal is formed from a combination of the input signals.Type: GrantFiled: February 11, 2004Date of Patent: November 11, 2008Assignee: Analog Devices, Inc.Inventor: James C. Camp