Patents Represented by Attorney, Agent or Law Firm Lanny L. Parker
  • Patent number: 7483296
    Abstract: A memory device is proposed. The memory device includes a plurality of memory cells, wherein each memory cell includes a storage element and a selector for selecting the corresponding storage element during a reading operation or a programming operation. The selector includes a unipolar element and a bipolar element. The memory device further includes control means for prevalently enabling the unipolar element during the reading operation or the bipolar element during the programming operation.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: January 27, 2009
    Inventors: Ferdinando Bedeschi, Fabio Pellizzer, Augusto Benvenuti, Loris Vendrame, Paola Zuliani
  • Patent number: 7221913
    Abstract: An algorithm identifies a line-of-sight (LOS) signal that may be used to provide an effective time-of-arrival (TOA) estimation.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: May 22, 2007
    Assignee: Intel Corporation
    Inventors: Stuart A. Golden, Jong-Kae Fwu
  • Patent number: 7176842
    Abstract: A slot antenna having one or more electronic components attached across a slot of the antenna to provide either an RF open or an RF short based on the bias supplied to a control terminal of the electronic component. The antenna is tunable via the RF open or short across the slot.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventors: Allen W. Bettner, Xintian E. Lin, Alan E. Waltho
  • Patent number: 7177293
    Abstract: A telecommunications system supports a variety of packet data services with throughputs ranging from low to high data rates. The system controls the user data transmission over a channel according to the user data throughput requirements of the application. By properly scheduling the time that particular transmission takes place, high data rate applications may be supported without the need for code aggregation, and low rate users may be supported without the requirement of multiple spreading factors. Base stations may transmit scheduling information to user devices in downlink time slots and user devices may transmit status information to base stations in uplink time slots.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventor: Carl Mansfield
  • Patent number: 7133970
    Abstract: A dynamic cache-locking algorithm may determine the most frequently used function(s) and the number of cache lines that should be locked into the instruction cache embedded into a processor. By evaluating the dynamic cache-locking algorithm, a determination may be made to lock an optimal amount of functions that correspond to a given, limited amount of instruction cache.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: November 7, 2006
    Assignee: Intel Corporation
    Inventors: Priva N. Vaidya, Moinul H. Khan
  • Patent number: 7069042
    Abstract: A tone generator in a transceiver of a communications device may generate an arbitrary signal using two shift registers to generate the time intervals. During each time interval, a different capacitor is switched onto the node to change the voltage potential on that node. The amplitude of the waveform during each time interval is changed to provide the desired tone.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: June 27, 2006
    Assignee: Intel Corporation
    Inventor: Luiz Franca-Neto
  • Patent number: 7054218
    Abstract: A decode circuit for a memory that uses “sequential addressing” includes a series of decoders form a shift register that may be used to provide either wordlines or column select lines for accessing the memory. A pulse generator supplies an appropriate number of pulses to the series of decoders in accordance with a difference in a stored previous address and a received current address.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: May 30, 2006
    Assignee: Intel Corporation
    Inventor: Chen Gu
  • Patent number: 7013133
    Abstract: Briefly, in accordance with one embodiment of the invention, a portable computing or communication device includes a classmark. A first network may poll the portable communication device and alter the classmark, and thus, alter how a second network interacts with the portable communication device.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: March 14, 2006
    Assignee: Intel Corporation
    Inventor: Matthew A. Hayduk
  • Patent number: 7010706
    Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit has a voltage regulator that is used to provide a power supply potential to a memory circuit while a logic circuit is decoupled from a power supply potential.
    Type: Grant
    Filed: April 13, 2001
    Date of Patent: March 7, 2006
    Assignee: Intel Corporation
    Inventors: Lawrence T. Clark, Neil F. Deutscher, Eric J. Hoffman
  • Patent number: 6976117
    Abstract: A processor system having cache array for storing virtual tag information and physical tag information and corresponding comparators associated with the array to determine cache-hits. Information from the virtual tag array and the physical tag array may be accessed together.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: Lawrence T. Clark, Dan W. Patterson, Stephen J. Strazdus
  • Patent number: 6975846
    Abstract: Briefly, in accordance with an embodiment of the invention, a method and circuit to reduce intermodulation distortion is provided, wherein the method includes receiving a baseband signal and an interferer signal located in a frequency band and attenuating the interferer signal to reduce intermodulation distortion in the frequency band, wherein the attenuating occurs prior to anti-alias filtering of the baseband signal.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: Tsung Yuan Chang, Waleed Khalil, Bobby Nikjou
  • Patent number: 6944713
    Abstract: A processor having an L1 cache memory that may use a compare circuit to determine matches of stored tag information against an address and gate sense amps of the cache memory with a cache-hit signal.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: September 13, 2005
    Assignee: Intel Corporation
    Inventors: Lawrence T. Clark, Jay B. Miller
  • Patent number: 6925015
    Abstract: Briefly, in accordance with one embodiment of the invention, a system includes a memory array. The memory array comprises a first layer of memory cells overlying a second layer of memory cells and bit lined coupled to at least one memory cell in the first layer of memory cells and to at least one memory cell in the second layer of memory cell.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: August 2, 2005
    Assignee: Intel Corporation
    Inventors: John I. Garney, David G. Chow, Rick Coulson
  • Patent number: 6914289
    Abstract: An integrated circuit having a non-volatile HGRAM cell includes a first section having impurity materials implanted into a substrate to form NPN transistor regions and a second section having a gate structure to control the currents conducted in the NPN transistor regions. The gate structure is formed at least above the P-type channel region of the substrate and includes an hourglass shaped material with gates to control the movement of holes through the restricted portion of the hourglass.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: July 5, 2005
    Assignee: Intel Corporation
    Inventor: Kevin W. Bross
  • Patent number: 6879807
    Abstract: A system is disclosed having a remote access unit and two transceiver modes, one for implementing wireless wide area network communications and another for implementing local wireless network communications. High speed data communications with a cellular system may be maintained in the wireless wide area network mode with the advantage of a flexible and unconstrained remote access unit, which can be placed for improved wireless reception. Computers and other devices with complementary wireless personal network communications protocol units may connect to a wireless wide area network through the remote access unit.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: April 12, 2005
    Assignee: Intel Corporation
    Inventors: Brian L. Fox, John K. Reece
  • Patent number: 6842133
    Abstract: A system for two processors communicating though unidirectional links by embedding a strobe signal into the data by providing differential signals with different common mode signal levels.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: January 11, 2005
    Assignee: Intel Corporation
    Inventors: Ernest E. Woodward, Malcolm H. Smith
  • Patent number: 6801470
    Abstract: A self-adjusting circuit provides a reverse body bias to circuitry in a DROWSY mode. Memory cells having the appropriate skews are supplied with a changing operating voltage potential, causing a memory cell to fail and determining the correct back bias potential VSS to supply that improves operation of the processor in a low power standby mode.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: October 5, 2004
    Assignee: Intel Corporation
    Inventors: Lawrence T. Clark, Neil F. Duetscher
  • Patent number: 6795877
    Abstract: A system includes an application processor and a baseband processor that may be configurable to communicate by the transfer of data in a hexadecimal format, an octal format or a decimal format in accordance with programmed bits in a register's data field.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: September 21, 2004
    Assignee: Intel Corporation
    Inventor: Scott C. Glenn
  • Patent number: 6791889
    Abstract: A system supports Double Date Rate (DDR) or Single Data Rate (SDR) data transfers on a data bus between a processor and a memory device. A controller-side interface block connects to a memory-side interface block for generating the control signals and transferring stored data from the memory device to the processor.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: September 14, 2004
    Assignee: Intel Corporation
    Inventor: Steve A. Peterson
  • Patent number: 6775180
    Abstract: An integrated circuit having a state retentive memory structure to store state values. A high performance section uses thin gate-oxide transistors and the state retentive memory structure uses thick gate-oxide transistors to capture and retain the state values when operating in a low power mode.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: August 10, 2004
    Assignee: Intel Corporation
    Inventors: Manish Biyani, Lawrence T. Clark, Shay P. Demmons, Franco Ricci