Abstract: An integrated circuit having a state retentive memory structure to store state values. A high performance section uses thin gate-oxide transistors and the state retentive memory structure uses thick gate-oxide transistors to capture and retain the state values when operating in a low power mode.

Abstract: An integrated circuit having CMOS domino logic arranged in multistages or a tree structure. The multistage cells and addressing structure may have applications in a decoder and reduce the number of cells being precharged and reduce the operating power.

Abstract: A wafer carrier (300) for a CMP tool is adjustable to provide center fast to edge fast material removal from a semiconductor wafer. The wafer carrier (300) holds the semiconductor wafer without vacuum. The semiconductor wafer is held by a carrier ring (308). An elastically flexed wafer support structure (318) is a support surface for the semiconductor wafer. Elastically flexed wafer support structure (318) can be bowed outward or bowed inward in an infinite number of different contours. The semiconductor wafer conforms to the contour of the elastically flexed wafer support structure (318) when a down force is applied to the wafer carrier (300) during a polishing process. Changing the contour is used to produce different material removal rates across the radius of the semiconductor wafer to increase wafer planarity in a polishing process.

Abstract: A radio frequency (RF) switch (40) for use in a wireless communication system operated in a time delay division mode of operation. The switch includes a pair of PIN diodes (54 and 56) serially coupled between the transmitter and receiver paths of the communication system which share a common node (58) to which a bias voltage is provided. The bias voltage is switched between first and second voltage levels to alternately cause one and the other of the pin diodes to be forward biased while the other is reversed bias. In this manner the transmitter and receiver paths will be alternately shorted to alternating current ground while the other path is shorted to a common node to an antenna.

Abstract: A digital video encoder (16) receives a reference clock signal (REF_CLK27) for determining both a short term and a long term phase correction factor. A pulse detector (46) determines a number of sample clock (CLK324) time periods between the reference clock signal (REF_CLK27) and a clock signal (CLK27) that is derived from the data received by the digital video encoder (16). A phase increment generator (56) supplies an accumulator circuit (58) with a long term phase increment value based on the number of sample clocks and a TV_standard signal. A counter (60) and a phase look-up table (62) supply a short term increment value. The combined short term and long term increment values provide phase and frequency accuracy for the video subcarrier signal.

Abstract: In a Huffman decoder, a data structure for storing Huffman codes includes a first field for storing a 0-way code and a second field for storing a 1-way code. A first flag is associated with the first field and indicates whether the first field stores an index adjustment or a Huffman code result. A second flag is associated with the second field and indicates whether the second field stores an index adjustment or a Huffman code result.

Abstract: A plurality of serially coupled circuit cells (12-20) are modeled as a distributed serial load. The distributed serial load provides an accurate load model in situations where one cell is effected by loading on subsequent circuit cells, i.e. downstream loading is conveyed back to the first cell. The capacitance (22) and resistance (24, of each cell has a loading effect on each previous cell. The effective resistance and capacitive values of each cell is identified and maintained as one element of the distributed serial load model. The distributed serial load accurately models the loading of unbuffered cells (16-20). The distributed serial load is also applicable to portions of circuit cells (38,40) that are not be buffered and where the downstream loading has an effect on previous circuit drivers (14).

Abstract: A micro electro-mechanical systems device having variable capacitance is controllable over the full dynamic range and not subject to the “snap effect” common in the prior art. The device features an electrostatic driver (120) having a driver capacitor of fixed capacitance (121) in series with a second driver capacitor of variable capacitance (126). A MEMS variable capacitor (130) is controlled by applying an actuation voltage potential to the electrostatic driver (120). The electrostatic driver (120) and MEMS variable capacitor (130) are integrated in a single, monolithic device.

Abstract: A sensor (10) includes a cavity (31) formed by a substrate (11), an adhesive (21), and a filter (22). A sensing element (14) is located inside the cavity (31) while electrical contacts (17, 18) coupled to the sensing element (14) are located outside the cavity (31). The filter (22) protects the sensing element (14) from physical damage and contamination during die singulation and other assembly processes. The filter (22) also improves the chemical sensitivity, selectivity, response times, and refresh times of the sensing element (14).

Abstract: A sensor has an electrode (120) that is movable along three mutually perpendicular axes (10, 11, 12). The sensor also has stationary over-travel limiting structures that restrict the movement of the electrode (120) along the three axes (10, 11, 12).

Abstract: A sense amplifier circuit (10) utilizes two current mirror amplifiers (11, 12) to determine the state of the memory cell. Multiple current mirrors are used in order to determine which of four possible states are stored in the memory. A reference circuit (38, 41, 43) uses the same transistor structure that is in the memory to improve the operational reliability.

Abstract: A circuit (300) for reducing Moiré effects in a display by delaying in alternate horizontal display lines a received horizontal drive pulse (HDRV IN), the circuit having: a current source arrangement (304, 314.1-314.n, 316.1-316.n) for tracking the display scanning speed and for producing a current which is representative of a binary input value (DVAL); a capacitor (308) arranged to be charged by the current; and a comparator (310) connected to the capacitor for delaying the received horizontal drive pulse by an amount dependent on the rate of charging of the capacitor. The circuit provides auto tracking with display scanning speed and programmability of the delay value. The circuit can be fabricated in integrated circuit form.

Abstract: A method for executing instructions on an application-specific microprocessor having a machine language is described. Microcontroller-like instructions are provided in a virtual language for execution on the processor. High-level DSP-like functions are compiled into DSP-like instructions in the machine language for execution on the processor. The microcontroller-like instructions are combined with the DSP-like instructions to produce a program, the program having a virtual language portion and a machine language portion respectively. When the program is executed, the virtual language portion of the program is translated into machine language instructions, and the machine language portion of the program is directly executed, such that the application-specific microprocessor executes both the DSP-like instructions and the microcontroller-like instructions.

Abstract: An electrode structure for semiconductor devices includes first electrode material positioned in overlying relationship to the surface of a substrate so as to define a first side wall perpendicular thereto. A nonconductive side wall spacer is formed on the first side wall and defines a second side wall parallel to and spaced from the first side wall. Second electrode material is formed in overlying relationship to the substrate and on the second side wall so as to define a third side wall parallel to and spaced from the second side wall. The first and second electrode materials are connected as first and second electrodes in a common semiconductor device. Additional electrodes can be formed by forming electrode material on additional side walls.

Abstract: A transceiver (10) includes a transmitter (16) that receives a digital data stream from a digital signal processor (18) to delay lines (20, 30). The delay lines (20,30) provide an address to a ROM look-up table (40). Another input of the look-up table (40) receives a signal that selects protocols such as TDMA, CDMA, and GSM. A multi-accumulator fractional-N synthesizer (48) receives phase derivative coefficients and a DAC (46) receives amplitude modulation coefficients from the look-up table (40) based on the selected protocol. The analog output signals from the DAC (46) and the synthesizer (48) are received by a variable gain amplifier (54) that generates an RF amplitude and frequency modulated output signal for transmission from the transmitter (16). The look-up table (40) stores phase derivative coefficients and amplitude modulation coefficients that correct for non-linearity in the variable gain amplifier (54).

Abstract: An improved logarithmic amplifier (100) and method in which a signal at an output (106) is logarithmic with respect to the voltage supplied at a gain control input (102). The logarithmic amplifier (100) includes a first amplifier stage (110) and a second amplifier stage (130) which are coupled together by a current mirror stage (120). Alternative embodiments of logarithmic amplifier (200) and (300) include different biasing methods for biasing the second amplifier stage (130).

Abstract: A portable electronic device such as a mobile telephone is powered by a battery and is arranged to operate in an off-mode, a standby mode and an on-mode of operation. Primary electronic circuitry, operable only during the on-mode, provides the main features of the device. Secondary electronic circuitry is operable during the off-mode, and standby circuitry is operable during the standby mode. A power supply circuit is arranged for coupling to the battery in order to provide power to the electronic device during the on-mode. A secondary power source is arranged to be charged by the power supply circuit during the on-mode and further arranged for providing power to the second electronic circuitry during the off-mode. The secondary power source is further arranged for providing power to the standby circuitry during the standby mode, such that the power supply circuit does not operate during the standby mode.

Abstract: A differential capacitor structure (10) formed overlying a substrate (12) having a middle layer (24) disposed between a lower layer (18) and an upper layer (28). The lower layer (18) is a static layer that is formed on the substrate (12), the middle layer (24) has a moveable component and is a dynamic layer attached to the substrate (12) using semi-circular tether supports (42), and the upper layer is a static layer that is anchored to the substrate (12). The semi-circular tether supports (42) are formed from a homogeneous material and provide structural stiffness to support the middle layer (24) in space and also provide stress relief.

Abstract: A direct modulation multi-accumulator fractional-N frequency synthesizer 1 for generating a carrier signal 150 modulated by a modulation signal 170, 121 is disclosed. The frequency synthesizer includes a Voltage Controlled Oscillator, VCO 50, having a tuning port for controlling the frequency of the signal 110 output by the VCO, a variable divider 20 and a multi-accumulator sequence generator 21 for controlling the variable divider, a reference signal generator 50, a phase detector 30 and a low pass filter 40. These elements are arranged to form a Phase Locked Loop arrangement, the directly modulated output signal of which is taken from the output of the VCO, wherein in-band modulation is performed by varying the variable divider and out-of-band modulation is performed by directly applying the modulating signal to the VCO tuning port.

Abstract: A wet etch bath (61) holds a wet etchant (52) for etching a dielectric over a semiconductor substrate. The wet etch bath (61) has a tub (63) separated from a reservoir (64) by a wall (65). The tub (63) is filled with the wet etchant (52) to a height of the wall (65). The reservoir (64) is filled with the wet etchant (52) to a height less than the height of the wall. A pump (66) coupled to the reservoir (64) pumps the wet etchant (52) through an osmotic membrane degasifier (69) to the tub (63). Adding the wet etchant (52) to the tub (63) causes the wet etchant (52) to cascade over the wall (65) back to the reservoir (64). The osmotic membrane degasifier (69) reduces a concentration of a reactive agent in the wet etchant (52).