Abstract: A connector and tubing assembly including a multi-lumen molded connector having at least three flexible tubes also molded into the connector. The connector may be “Y” shaped and include three flexible tubes. A process of making the connector and tubing assembly involves forming a first part of the connector with two tubes molded therein and then removing an internal mold member prior to molding the final connector portion and third tube in place.
Abstract: A data processing system (100) comprises a system bus (120), a plurality of devices (110, 150, 160, 170) coupled to the system bus (120), a bus monitor circuit (140), and a clock generator (130). The plurality of devices (110, 150, 160, 170) includes at least one bus master (110, 150) which is capable of performing accesses on the system bus (120). The bus monitor circuit (140) is coupled to the at least one bus master (110, 150), and has an output for providing a bus idle signal to indicate that no bus master is attempting to perform an access on the system bus (120). The clock generator (130) has an output coupled to at least one of the plurality of devices (110, 150, 160, 170) and provides a bus clock signal having a first frequency when the bus idle signal is inactive and having a second frequency lower than the first frequency when the bus idle signal is active.
Type:
Grant
Filed:
October 30, 2002
Date of Patent:
August 15, 2006
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Richard T. Witek, Suzanne Plummer, James Joseph Montanaro, Stephen Charles Kromer, Kathryn Jean Hoover
Abstract: In one embodiment, the disclosure is directed to a chemical mechanical polishing retaining ring. The chemical mechanical polishing retaining ring includes a support formed of a first material comprising a first polymer and a wear portion formed of a second material comprising a second polymer. The first material has an elastic modulus greater than the elastic modulus of the second material.
Abstract: A method of coating a substrate for a high temperature superconductor material is disclosed, including loading a substrate into a first deposition chamber, routing the substrate in the first deposition chamber such that the substrate forms a helical winding in the first deposition chamber, and depositing a first buffer layer to overlie the substrate as the substrate translates along the helical winding. The buffer layer has a biaxial crystallographic texture.
Abstract: A superconductor article includes a substrate and a first buffer film disposed on the substrate. The first buffer film includes a polycrystalline material. An IBAD (ion-beam assisted deposition) second buffer film is disposed on the first buffer film, the second buffer film having a biaxial crystal texture. A superconductor layer can be disposed on the second buffer film.
Abstract: A superconducting article includes a first superconductive segment having a nominal thickness tn1, a second superconductive segment having a nominal thickness tn2, and a joint region comprising a splice connecting the first and second superconductive segments together. The splice overlies portions of both the first and second superconductive segments along the joint region, the joint region having a thickness tjr, wherein tjr is not greater than at least one of 1.8 tn1 and 1.8 tn2.
Type:
Grant
Filed:
April 8, 2005
Date of Patent:
July 4, 2006
Assignee:
Superpower, Inc.
Inventors:
Venkat Selvamanickam, Yi-Yuan Xie, Allan Robert Knoll
Abstract: A buffer (40) includes a capacitor (42) having a first terminal for receiving an input signal, and a second terminal; a first transistor (44) having a first current electrode for receiving a first power supply voltage, a control electrode coupled to the second terminal of the capacitor (42), and a second current electrode for providing an output signal of the buffer (40); and a second transistor (45) having a first current electrode coupled to the second current electrode of the first transistor (44), a control electrode coupled to the second terminal of the capacitor (42), and a second current electrode for receiving a second power supply voltage. A capacitance of the capacitor (42) is chosen to reduce a peak-to-peak voltage swing of the input signal such that a peak-to-peak voltage swing at the control electrodes of the first (44) and second (45) transistors is less than or equal to a difference between the first and second power supply voltages.
Type:
Grant
Filed:
March 25, 2004
Date of Patent:
June 20, 2006
Assignee:
Silicon Laboratories, Inc.
Inventors:
Scott D. Willingham, Augusto M. Marques
Abstract: A data processor (120) recognizes a special data processing operation in which data will be stored in a cache (124) for one use only. The data processor (120) allocates a memory location to at least one cache line of the cache (124). A data producer such as a data communication driver program running on a central processing unit (122) then writes a data element to the allocated memory location. A data consumer (160) reads the data element by sending a READ ONCE request to a host bridge (130). The host bridge (130) provides the READ ONCE request to a memory controller (126), which reads the data from the cache (124) and de-allocates the at least one cache line without performing a writeback from the cache to a main memory (170). In one form the memory controller (126) de-allocates the at least one cache line by issuing a probe marking the next state of the associated cache line as invalid.
Abstract: A horizontal wafer boat for maintaining semiconductor wafers during wafer processing is disclosed. The wafer boat is configured to reduce the likelihood wafer slip when wafers are heated to processing temperatures of about 1000° C. and above.