Abstract: An apparatus is presented and proved for detecting storage operand overlap for instructions having identical overlap detection requirements as the move character (MVC) instruction. The apparatus is applicable to all Enterprise Systems Architecture (ESA)/390 addressing modes encompassing access register addressing for either 24 bit or 31 bit addressing. S/370 addressing in 24 bit and 31 bit modes are also supported by the proposed apparatus and treated as special cases of access register addressing. In addition, the apparatus is extended to support other addressing modes with an example provided to include a 64 bit addressing mode. A fast parallel implementation of the apparatus is also presented. The apparatus results in a one cycle savings for all invocations of the MVC instruction which comprises approximately 2% of the dynamic instruction stream of a representative instruction mix.

Abstract: An edge detector has a digital phase locking loop in which one of the signals (e.g., the data signal) is coupled to a delay chain that develops a series of incrementally phase delayed versions of the input. Adjacent phase delayed pairs are selected, one pair at a time, and are compared to the other signal (e.g., the clock signal) to determine if an edge of the clock falls between the edges of the data signal in the selected phase pair, or falls outside the edges of the selected phase pair, on one side or the other thereof. If the clock edge falls outside the selected pair, a control signal selects another pair for comparison and the process is repeated until, for example, the data edges are aligned with the positive going edge of the clock. With a clock frequency equal to twice data frequency, the data can then be sampled on the falling edge of the clock.

Abstract: A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured and an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link.

Abstract: A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit.

Abstract: In a digital computer system both rotation of bits in a data byte and rotation in combination with additional manipulation, a multifunction permutation switch, in a cyclic mode of operation, connects the input bit lines to the output bit lines so that the sequence of input bits are maintained on the output bit lines when the bits on the input lines are considered as arranged in a circle, and in a non-cyclic mode of operation, connects the input bit lines to the output bit lines in a manner to execute gather operations and spread operations.

Abstract: A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and generating for to each instruction a compounding information which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit with the compounding information. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit.

Abstract: A digital computer system capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with another neighboring instruction. Tagged instructions are stored in the main memory. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to the functional units are obtained from the memory by way of a cache storage unit. At instruction issue time, the tag fields of the instructions are examined and those tagged for parallel processing are sent to different ones of the functional units in accordance with the codings of their operation code fields.

Abstract: A mechanism for controlling the powering-on and powering-off of control units in a data processing system having a plurality of channels, a plurality of control units, and a communications network of links for linking the channels to the control units. Each control unit includes a power-control table for recording power-control allegiance of the control unit to the channels. Where a control unit receives a power-on command from a channel, it records the identity of the channel in its power-control table. When a channel orders a control unit to power-off, the control unit checks to see if it owes power-control allegiance to the ordering channel. If it does, the control unit deletes the identity from its power-control table. The control unit will not power-off unless its power-control table is empty, indicating that it does not owe allegiance to any other channel.

Abstract: A system with an apparatus that can be used in the compounding of instructions for CISC architectures and architectures with other attributes, including RISC. The compounding is performed before instruction execution and it results in a compound instruction program that can be executed in a parallel fashion on appropriate instruction execution hardware. In particular, the proposed apparatus provides compounding capability for architectures that allow the intermingling of instructions and data, contain variable length instructions, and allow modifications of the instruction stream. The system provides for differing and partial reference point information. An embodiment of the proposed apparatus handles the worst-case situation when it is not known which text bytes are instructions and which are data. If some information is known, the system can be simplified. The apparatus as presented provides compounds capability for any number of instructions.

Abstract: A system for compounding instructions across cache line boundaries transfers an instruction line from a relatively slow memory to a instruction compounding unit if there is a miss for an instruction in that line in the instruction cache. At the same time the numerically preceding instruction in cache is transferred to the instruction compounding unit and instructions from the two lines are compounded. If a numerically preceding cache line has been compounded with a cache line that has been deleted and then replaced, compounding tags for the numerically preceding cache line are deleted.

Abstract: A high speed three-to-one data dependency collapsing ALU can be used to support multiple issue of instructions. The computing apparatus supports multiple issue of instructions it is useful in CISC, superscalar, superscalar RISC, etc. type computer designs. The concept of the ALU is presented along with a detailed description of a design. The apparatus allows the execution of any combination of two independent or dependent arithmetic or logical instructions in a single machine cycle. The 3-1 collapsing ALU structure has a 3-2 carry save adder (CSA); and a 2-1 control arithmetic logic unit (CALU) coupled for an input from the carry save adder; and a first pre-adder logic block coupled with an output to the control arithmentic logic unit; and a control generator; and a second controlled logic block coupled to receive an input from said control generator and having its output coupled to said control arithmetic logic unit.

Abstract: Described is a Load Unit for processing the data fetch in load instructions. The Load Unit predicts the address for the data fetch such that the fetch can occur earlier than in the typical load processing. By processing the fetch early, the normal cache access cycle can be eliminated reducing overall execution time. Cache misses can be processed in parallel with other execution thereby reducing the performance degradation of cache misses.

Abstract: Briefly, this invention contemplates the provision of a call pacing method in which the number of calls to dial is periodically (e.g. every two seconds) determined on the basis of anticipated operator availability. The determined number of calls are dialed, subject to a limiting function. Calls in progress are interrupted in a short time slot just prior to first ring if the number of operators available to respond to an answered call falls below a predetermined percentage of the total number of system operators.

Abstract: A holding fixture with five discrete vacuum elements provides support at four peripheral points on a substrate and at the substrate center. Two peripheral vacuum elements are fixed in position on a rigid frame. The remaining peripheral elements and the center element are fixed to a gimbal disc. This gimbal disc is mounted on the frame in such a way that it has three degrees of rotational movement relative to the frame. Downward pressure of a substrate resting on the two fixed elements, brings all three gimbal disc mounted supports into contact with the substrate, without allowing or causing deflection of the substrate. The mounting is locked, and vacuum is applied to all the elements to secure the substrate in place for the planarizing operation.

Abstract: A low-cost test system for testing digital circuit elements, such as a memory array, which includes a base to provide operating voltage and an operator interface in combination with interchangeable, removable test modules. Each test module includes a test function data processor, an address generator for selecting addresses to be tested, and a comparator for comparing actual output signals with the generated expected outputs. The test function data processor has a number of stages of high-speed memory and logic to generate independently test program data, test program expected data and test address control data.

Abstract: A current interrupter in which a first movable, insulating, gear carries a contact blade. The blade extends out from this movable gear and forms a contact which makes and breaks with a stationary contact upon movement of the gear. A second insulating gear has a set of teeth which engage the teeth on the first gear. The second gear has a cavity into which the extended contact fits. Movement of the first gear in a direction to break the contact, causes the engaged teeth to drive the extended contact into the cavity, thereby insulating the movable contact from the stationary contact. The interlocking gear teeth create a tortuous path for the arc and provide a large over surface distance for dielectric strength.

Abstract: A computer control system in which each input condition to which the system must respond is defined and a priority value assigned thereto. Desired system resource conditions called attributes herein corresponding to each input are determined. System resource states or attributes for all combinations of control element states are determined. An optimum configuration for the discrete control elements is established for a set of input conditions by comparing the system resource condition for each control element configuration with the system resource condition desired for all the input conditions. A score for each input condition is determined based on the priority of the input condition and the number of resource conditions for the input condition which match the resource conditions for a control elements configuration, and the optimum control configuration is the configuration which produces the highest cumulative score for all input conditions.

Abstract: In a regulated power supply, particularly a pulse-width-modulated supply, the on-off control is located in the feedback path between the supply output terminal and the pulse-width-modulator. Transformer coupled polling pulses sense both the state of the on-off control and the magnitude of the feedback error signal.

Abstract: A mounting method for printed circuit boards provides improved electromagnetic interference reduction while minimizing the required number of mounting screws. A conductive base plate formed with supporting members is configured to mate with a grounding circuit on the board. A central mounting screw places the board in compression to provide electrical continuity between the grounding circuit and the supporting members of the conductive plate.

Abstract: A system for controlling an activity (program) switch on a scientific processor having an external executive control program. It includes the sequencing of the hardware at a macro level rather than at the more detailed lower levels previously used. This sequencing and control is accomplished by providing a macro code control, a macro code store and an instruction buffer write data selector interconnected with the existing macro logic and the main storage of the scientific processor to provide a system for starting, running and stopping the scientific processor by an activity switch which responds to interrupt signals to selectively shift from the receipt of data from the main storage to the receipt of data from the macro code store.