Abstract: A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.

Abstract: A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

Abstract: A cross descriptor learning system, method and program product therefor. The system extracts descriptors from unlabeled exemplars. For each unlabeled exemplar, a cross predictor uses each descriptor to generate labels for other descriptor. An automatic label generator also generates labels for the same unlabeled exemplars or, optionally, for labeled exemplars. A label predictor results for each descriptor by combining labels from the cross predictor with labels from the automatic label generator.

Abstract: A selectively synchronous wave pipeline segment and an integrated circuit (IC) including the segment. The segment includes a normally opaque input stage and output stage and multiple internal stages that are normally transparent. A programmable local clock control circuit provides internal stage clock selection control to internal stages. The internal clock selection control determines whether each internal pipeline stage is gated opaque by a local clock. The programmable local clock control circuit is programmed to allows data items to propagate as data waves in a wave pipeline until each wave reaches a point where beyond, a race condition is likely to exist. Multiple pipeline data items pass as data waves between input and said output stage selectively unclocked.

Abstract: A self healing ad hoc communications network and method of training for and healing the network. The network includes wireless devices or nodes that include a neural network element and the ad hoc network operates as a neural network. Some of the nodes are designated as healing nodes that are identified during network training and are strategically located in the network coverage area. Whenever one group of nodes loses connection with another a healing node may reposition itself to reconnect the two groups. Thus, the network can maintain connectivity without constraining node movement.

Abstract: A printer and method of managing print jobs in the printer. Print job locations are identified in the printer. Each print job being printed is always in at least one of the print job locations and the locations are monitored for entering and exiting jobs. The printer includes a job location mask for each print job. Each bit location in the job location mask corresponds to one of the print job locations and a set bit indicates the presence of a print job in a corresponding print job location. As a print job enters a location, the location issues a call and the job location mask is updated to reflect the presence of the print job in that location.

Abstract: A method of physical design for integrated circuit (IC) chip fabrication, physical design system and program product therefor. A design shape is fragmented into segments for Optical Proximity Correction (OPC) and a harmonic mean of the segments is determined. Electrical intent is determined for the shape and a harmonic mean is determined for the segments. Segments may be moved based on a effect on the harmonic mean from moving the segments, measured using a harmonic mean cost function. Finally segmented shapes are passed to OPC.

Abstract: A temperature tolerant hook and loop attachment, a method of forming a sheet of the hooks and, a method of insulating the skin of a flight vehicle. Temporary loops are formed in a fabric containing temperature tolerant fiber tows, e.g., the tows may be carbon, a metal, a carbide such as carbon silicide, a nitride, or an oxide. The temporary loops are stiffened (e.g., with resin, metal or ceramic), and severed to form temperature tolerant fiber composite hooks. The sheet may be cut and permanently applied, for example, to the skin of a spacecraft or aircraft. A fibrous material, e.g., fibrous insulation or batting, may be pressed in place or formed into the hooks, or the fibrous material may be attached to another structure and pressed in place for a temperature tolerant hook and loop attachment.

Abstract: A proactive problem resolution system, method of proactive problem resolution and program product therefor. User sensors extract data from user interaction with a computer terminal and pass extracted data to a sniffer agent. The sniffer agent checks for an indication of a user problem by comparing user behavior data against behavior data from previously encountered problems. When the sniffer finds a match, the computer terminal user may be asked if assistance is needed or the user may be automatically referred to the help desk. If a solution already exists for a problem that corresponds to the user behavior, that solution(s) is(are) presented at the computer terminal. Computer terminal users automatically receive problem support, even before it would otherwise be requested.

Abstract: An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

Abstract: A stylus, an integrated circuit (IC) and method of forming the IC. The stylus extends upward from its apex and has a substantially circular cross section that decreases in diameter upward from the apex. The stylus is formed in a mold that may be formed in an orifice in a dielectric layer between wiring layers. The mold may include multiple concentric layers. For a more pronounced, non-linear stylus taper, each layer may be thinner than its next adjacent outer concentric layer.

Abstract: A fastening assembly for a composite structure including a washer sealing the assembly for internal lightning strike protection. The washer includes one or more concentric ribs that are dielectric rings on both sides. When used (e.g., with a nut and bolt) internal to a structure, especially a composite structure, the washer seals the fastener hole (i.e., that the bolt passes through) and contains any sparking and hot gasses that may arise in the fastener hole from entering the structure.

Abstract: A storage subsystem, method of automatically maintaining the subsystem hardware configuration up to date and program product therefor. The storage subsystem automatically initiates hardware discovery in response to a triggering event. Subsystem hardware information is collected during hardware discovery and checked against a current configuration to identify hardware changes. Whenever hardware changes are identified, the subsystem configures the hardware and calibrates newly configured hardware. So, hardware changes may be automatically discovered, configured and calibrated free from operator intervention.

Abstract: A storage cell, integrated circuit (IC) chip with one or more storage cells that may be in an array of the storage cells and a method of forming the storage cell and IC. Each storage cell includes a stylus, the tip of which is phase change material. The phase change tip may be sandwiched between an electrode and conductive material, e.g., titanium nitride (TiN), tantalum nitride (TaN) or n-type semiconductor. The phase change layer may be a chalcogenide and in particular a germanium (Ge), antimony (Sb), tellurium (Te) (GST) layer.

Abstract: A stylus, an integrated circuit (IC) and method of forming the IC. The stylus extends upward from its apex and has a substantially circular cross section that decreases in diameter upward from the apex. The stylus is formed in a mold that may be formed in an orifice in a dielectric layer between wiring layers. The mold may include multiple concentric layers. For a more pronounced, non-linear stylus taper, each layer may be thinner than its next adjacent outer concentric layer.

Abstract: A method of integrated circuit (IC) design, an IC design system and computer program product therefore, e.g., for L3GO designs. Special case cells are cells that represent specialized, process dependent components and are provided as dual representation cells with an internal view and external view. The external view is high level abstract representation that includes access pins, boundary and possible blocking shapes/layers and optionally, parameterizations. Each external view includes cell to cell spacing rules and connecting and blocking/keepout rules for placement and routing. The internal representation or, internal view includes regular shapes forming cell components and defining cell construction details and are ground rule clean by construction or verified by simulation or hardware.

Abstract: A program product and method of managing task execution on an integrated circuit chip such as a chip-level multiprocessor (CMP) with Simultaneous MultiThreading (SMT). Multiple chip operating units or cores have chip sensors (temperature sensors or counters) for monitoring temperature in units. Task execution is monitored for hot tasks and especially for hotspots. Task execution is balanced, thermally, to minimize hot spots. Thermal balancing may include Simultaneous MultiThreading (SMT) heat balancing, chip-level multiprocessors (CMP) heat balancing, deferring execution of identified hot tasks, migrating identified hot tasks from a current core to a colder core, User-specified Core-hopping, and SMT hardware threading.

Abstract: A method of selecting a gateway node in a remote network and for handing over to the selected gateway node. Nodes in a remote energy aware network connect through a gateway node to a backbone network in an interplanetary communications network. Each node optimizes a stability function describing communications to neighboring nodes and to the backbone. Optimization is for maximum network stability and for efficient node energy consumption. Optimization identifies a handover time and nodes initiate handover sufficiently in advance of the identified handover time to complete at that time. Nodes continually monitor and update network characterization parameters to identify a next optimal handover time.

Abstract: A collision sense and avoidance system and method and an aircraft, such as an Unmanned Air Vehicle (UAV) and/or Remotely Piloted Vehicle (RPV), including the collision sense and avoidance system. The collision sense and avoidance system includes an image interrogator identifies potential collision threats to the aircraft and provides maneuvers to avoid any identified threat. Motion sensors (e.g., imaging and/or infrared sensors) provide image frames of the surroundings to a clutter suppression and target detection unit that detects local targets moving in the frames. A Line Of Sight (LOS), multi-target tracking unit, tracks detected local targets and maintains a track history in LOS coordinates for each detected local target. A threat assessment unit determines whether any tracked local target poses a collision threat. An avoidance maneuver unit provides flight control and guidance with a maneuver to avoid any identified said collision threat.

Abstract: A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.