Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.

Abstract: A method of managing an ad hoc communications network of wireless devices or nodes. The network is connected if all nodes can communicate with each other and otherwise partitioned. Partitions are identified by recursively applying a connectivity function to a connectivity matrix representative of the network. The number of times the connectivity function is recursively applied is determined by the network diameter. If the result of the recursive application is a unity matrix, the network is connected; otherwise it is disconnected. Also, if the network diameter exceeds a selected maximum length, the network may be voluntarily partitioned into connected sub-networks by recursively applying the connectivity function a lesser number of times to the connectivity matrix. The lesser number of times is determined by the selected maximum length or maximum allowable number of hops.

Abstract: An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

Abstract: A programmable, electrically alterable (EA) resistor, an integrated circuit (IC) chip including the EA resistor and integrated analog circuits using on-chip EA resistors. Phase change storage media form resistors (EA resistors) on an IC that may be formed in an array of parallel EA resistors to set variable circuit bias conditions for circuits on the IC and in particular, bias on-chip analog circuits. The bias resistance is changed by changing EA resistor phase. Parallel connection of the parallel EA resistors may be dynamically alterable, switching one or more parallel resistors in and out digitally.

Abstract: A method of replacing an existing part or parts on a structure such as an aircraft. The structure is inducted for modification. An existing part is removed and a new part is temporarily installed. Hole locations are digitally transferred to the new part, e.g., photographically captured in a three-dimensional coordinate measurement system, converted to targets printable in a laser projection system. Targets are laser projected or printed on the replacement part. Holes are drilled at each printed target. The holes drilled at printed targets match hole locations on the existing part. Then, the new/replacement part is permanently attached to the structure.

Abstract: A high speed optical channel including an optical driver and a photodetector in a CMOS photoreceiver. The optical channel driver includes a FET driver circuit driving a passive element (e.g., an integrated loop inductor) and a vertical cavity surface emitting laser (VCSEL) diode. The VCSEL diode is biased by a bias supply. The integrated loop inductor may be integrated in CMOS technology and on the same IC chip as either/both of the FET driver and the VCSEL diode. The photodetector is in a semiconductor (silicon) layer that may be on an insulator layer, i.e., SOI. One or more ultrathin metal electrodes (<2000 ?) on the silicon layer forms a Schottky barrier diode junction which in turn forms a quantum well containing a two dimensional electron gas between the ultrathin metal electrode and the Schottky barrier diode junction.

Abstract: A power control system with a pseudo-power up, an aircraft including the power control system and a method of controlling power in an aircraft. On-board wiring is protected from faults by electronic circuit breakers (ECBs), which may also control AC/DC electrical power supplies of on-board electrical/electronic equipment. A computer processor operating a user interface, e.g., a graphical user interface (GUI), through a display. An on-board store stores the GUI, other computer applications and the current state of each ECB, e.g., in a breaker state table. In a pseudo-power mode up, the stored circuit breaker state is available without providing power to the ECBs and, correspondingly to the coupled on-board electrical systems. When terminated, the system can power off, or proceed to normal power where each ECB is configured according to the breaker state table prior to providing power to protected systems.

Abstract: An ontology directory service tool, computer program product and method of automatically discovering ontology file categories. A web search unit searches a network (e.g., the Internet) for semantic data files, e.g., semantic web pages. A preprocessing unit generates an ontology file from the content of each identified semantic data file. A category discovery unit identifies a domain for each ontology file and provides training sets for training ontology file classification. A classification unit trained using the training sets, classifies ontology file instances into inherent ontology categories.

Abstract: A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage.

Abstract: An imaging sensor with an array of FET pixels and method of forming the imaging sensor. Each pixel is a semiconductor island, e.g., N-type silicon on a Silicon on insulator (SOI) wafer. FETs are formed in one photodiode electrode, e.g., a P-well cathode. A color filter may be attached to an opposite surface of island. A protective layer (e.g., glass or quartz) or window is fixed to the pixel array at the color filters. The image sensor may be illuminated from the backside with cell wiring above the cell. So, an optical signal passes through the protective layer is filtered by the color filters and selectively sensed by a corresponding photo-sensor.

Abstract: An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.

Abstract: A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.

Abstract: A self managed ad hoc communications network nodes and node mobility management. Nodes include an Artificial Neural Network (ANN) that determines connection to other network nodes. The ANN may use free space propagation link life estimation, inverse modeling for partition prediction, Stochastic Approximation, and/or coarse estimation. The node includes storage storing network tables and matrices indicating network connectivity and connection to other nodes. Also, a wireless communications unit provides for wireless communicating with other nodes.

Abstract: A cache memory that may include a content addressable memory, random access memory (CAMRAM) cache and method for managing a cache to reduce cache energy consumption. A cache buffer receives incoming data and buffers a storage array. The cache buffer holds a number of most recently accessed data blocks. In any access, cache buffer locations are checked before checking the storage array.

Abstract: An optically connectable circuit board and optical components mounted thereon. At least one component includes optical transceivers and provides an optical connection to the board. Electronic components may be directly connected to the board electrically or optically. Also, some electronic components may be indirectly connected optically to the board through intermediate optical components.

Abstract: A circuit design method, computer program product and chip design system embodying the method. A gate selected for static timing analysis (STA) from a circuit design. Initial performance characteristics (e.g., load and transition slew) are determined for the selected gate. A charge equivalent effective capacitance (CQeff) is determined for the gate from the initial performance characteristics. A gate delay is determined in a single pass for the gate using CQeff as an effective load for said selected gate. Optionally, if the total gate load capacitance (Ctot) exceeds CQeff by less than a minimum, the effective capacitance (Ceff) is determined and used for determining the gate delay instead.

Abstract: An optically connectable circuit board and optical components mounted thereon. At least one component includes optical transceivers and provides an optical connection to the board. Electronic components may be directly connected to the board electrically or optically. Also, some electronic components may be indirectly connected optically to the board through intermediate optical components.

Abstract: A model for modeling electromagnetic response in a conductor and in dielectric, a method of modeling the electromagnetic response in the conductor and dielectric and a program product therefor. Coupled supplies (delayed capacitive-current-controlled current sources or delayed inductance-voltage-controlled voltage sources) are low pass filtered in an electromagnetic model for the particular medium, e.g., a Partial Element Equivalent Circuit (PEEC) model for a conductor or dielectric. Thus, high frequency model instabilities are substantially reduced or eliminated.

Abstract: A storage subsystem such as an array of disk drives, method of managing disk drives in the storage subsystem and program product therefor. The storage subsystem may be a redundant array of independent disks (RAID) and the individual disks drives may be Self-Monitoring, Analysis and Reporting Technology (SMART) capable drives. When one of the drives gives an indication of an impending failure, a disk image of the failing disk is built on an available spare disk. Once the image is complete, the failing disk may be replaced without down time for rebuilding a failed disk.

Abstract: An optically connectable circuit board and optical components mounted thereon. At least one component includes optical transceivers and provides an optical connection to the board. Electronic components may be directly connected to the board electrically or optically. Also, some electronic components may be indirectly connected optically to the board through intermediate optical components.