Abstract: The present invention is a persulfate microetchant composition especially useful for removing impurities from copper surfaces during fabrication of microelectronic packages. The microetchant formulation is characterized by its ability to selectively clean copper in the presence of nickel, nickel-phosphorous and noble metal alloys therefrom. Furthermore, no deleterious galvanic etching occurs in this microetchant-substrate system so that substantially no undercutting of the copper occurs. The combination of high selectivity and no undercutting allows for a simplification of the microelectronic fabrication process and significant improvements in the design features of the microelectronic package, in particular higher density circuits. The persulfate microetchant composition is stabilized with acid and phosphate salts to provide a process that is stable, fast acting, environmentally acceptable, has high capacity, and can be performed at room temperature.

Abstract: A multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections therebetween. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. Methods of making these structures have also been provided.

Abstract: A method and apparatus are disclosed for aligning an array of light transmitting elements to an array of photosensitive detectors. The array is adjusted along three axes. Any element (a coupled transmitting and detecting unit of the array) can be selected as the center of rotation. Small angular correction is made about the selected element by differentially moving the array in two axes, using adjustment tools. Alignment is accomplished by performing translational movement in the horizontal X and Y axes until a signal is detected. A rotational correction about the selected element is performed by moving one of a pair of adjustment devices until maximum light intensity is achieved for the end elements. Next, the array is scanned for the weakest performing element in the array. The alignment procedure is repeated until the performance of all of the elements in the array fall within a pre-established specification range.

Abstract: An electronic package and information handling system utilizing same wherein the package substrate includes an internally conductive layer coupled to an external pad and of a size sufficiently large enough to substantially prevent cracking, separation, etc. of the pad when the pad is subjected to a tensile pressure of about 1.4 grams per square mil or greater.

Abstract: A circuitized substrate assembly and method for making same wherein the assembly includes individual circuitized substrates bonded together. The substrates each include at least one opening, only one of which is substantially filled with a conductive paste prior to bonding. Once bonded, the paste is also partially located within the other opening to provide an effective electrical connection therewith.

Abstract: The present invention teaches a simplified process for fabricating high density printed wiring boards using a semi-additive process. Steps required to achieve this objective include adhering an electroless plated copper commoning layer to a surface roughened dielectric substrate. Subsequently, the commoning layer is photolithographically personalized by covering the commoning layer with a resist and then uncovering predetermined areas of the aforementioned commoning layer. Consequently, the semi-additive method involves electroplating copper onto the uncovered areas of the commoning layer, thereby generating copper features and circuitry. Finally, the semi-additive process requires the stripping of the remaining photoresist, and the unplated electroless copper layer is etched in order to electronically isolate the copper features and circuitry lines.

Abstract: Semiconductor chip structures are provided with embedded thermal conductors for removing heat from one or more electrically conductive circuit members thereof, wherein the circuit members are formed on one or more dielectric layers above a substrate, each layer having a low dielectric constant and a low thermal conductivity. One or more cooling posts, for example, multiple thermally conductive plugs, are selectively disposed within the semiconductor chip structure adjacent to one or more electrically conductive members and thermally coupled thereto so that heat produced by the members is transferred into and through the cooling posts for forwarding to the substrate and/or to an upper surface of the semiconductor chip structure. The backside of the substrate has a thermal sink thermally coupled thereto and electrically isolated from the substrate.

Abstract: Optical packages and a method of fabricating same, wherein an active optical device can be located relative to a substrate and coupler. The structure includes a substrate having electrical contact pads and alignment pads with precision aligned through-holes for at least one optical fiber. The optical fibers are supported by a housing, or coupler, having alignment pins that are precision located relative to the through-holes in the substrate and the optical fiber. A die, or active optical device, with one or more active optical elements on a first die surface and electrical contacts on a second die surface, is aligned with the electrical pads of the substrate and the active optical elements. The method incorporates the steps of grinding alignment pins into metallic pads and grinding optical fibers in one pass and then aligning the active optical device and the optical fibers by using the surface tension of conductive adhesive liquid. The fibers are then bonded.

Abstract: A package is described that couples a twelve channel wide fiber optic cable to a twelve channel Vertical Cavity Surface Emitting Laser (VCSEL) transmitter and a multiple channel Perpendicularly Aligned Integrated Die (PAID) receiver. The package allows for reduction in the height of the assembly package by vertically orienting certain dies parallel to the fiber optic cable and horizontally orienting certain other dies. The assembly allows the vertically oriented optoelectronic dies to be perpendicularly attached to the horizontally oriented laminate via a flexible circuit.

Abstract: A method of making a circuit board (10) on which surface electronic components (15) are mounted during the method using a solder reflow process. The board comprises a circuit portion (12), a surrounding circumferential portion (13) and at least one elongated opening (14) formed in the surrounding circumferential portion substantially parallel to the direction that the board travels during the reflow direction (16), thereby preventing electronic component soldering failures that may occur as a result of the deflection of the circuit board during the reflow process.

Abstract: An electromagnetic shield device for printed circuit boards (PCBs) which, in one embodiment, is made of conductive material and comprised of two parts. In another embodiment, the device is a singular element. In both examples, press-fit or compliant pins may be used to electrically couple the device to the PCB's ground layer. Alternatively, projecting pins or flat conductive plates can be used to provide this coupling. The device is also adjustable to accommodate PCBs of varying thicknesses. The device provides for added PCB stiffness while assuring prevention of electromagnetic radiation from the PCB's edge.

Abstract: A method for providing a package for a semiconductor chip that minimizes stresses and strains that arise from differential thermal expansion on chip-to-substrate or chip-to-card interconnections. A collar element of one or more elements is provided. Adhesive material connects the collar element to the electric device and to the substrate that supports it, forming a unitary electrical package.

Abstract: An interconnect structure having an increased chip connector pad and plated through hole density is provided. In particular, the interconnect structure includes a substrate having at least one plated through hole therein, and a first conductive layer sealing the at least one plated through hole. The substrate includes a layer of dielectric material thereon. The dielectric layer includes at least one aperture selectively positioned directly over the at least one plated through hole. The substrate further includes a metal layer, at least a pair of conductive layers that can carry signals, and at least another pair of conductive layers that can carry power, wherein the pair of conductive layers are shielded by the metal layer and the other pair of conductive layers.

Abstract: A contact assembly comprised of two parts bonded (e.g., welded) together, the first part including a male pin portion and the second part including a cylindrical jacket terminating in a flat end surface adapted for being electrically coupled (e.g., soldered) to a conductor (e.g., pad) on a substrate (e.g., PCB). Several contact assemblies may be positioned within a housing or substrate, to form a connector assembly which may then be positioned on and electrically coupled to a second substrate (e.g., a PCB), forming an electronic assembly.

Abstract: An optical coupler that provides for the direct mounting of integrated circuit(s). The coupler includes a two-part housing with grooves for accommodating optical fibers that are held in place when the two parts are put together. Circuitry is formed on the housing and solder balls, when heated to a liquid state and cooled (reflowed), are used to attach integrated circuit(s) onto the housing. At least one of these integrated circuit(s) is an optical die that is positioned in close proximity to the optical fibers to provide for the receipt and/or transmission of optical signals. The reflowing of the solder balls forms an electrical connection between the circuitry on the housing and the integrated circuit(s) and provides for alignment of these components. The housing is attached to a circuitized substrate using reflowed solder balls or wirebonds.

Abstract: An electronic board assembly carrying connectors on each side of its lower edge which is adapted to withstand the relatively strong forces required to insert or remove the assembly, e.g., from a backplane board, and yet provide many electrical contacts along the interconnection sites. The electronic board assembly comprises two symmetrical elementary PCBs electrically coupled together, each carrying a connector on its external lower edge. In one embodiment, these two PCBs are coupled together by a flexible adhesive insulative layer and maintained by mechanical devices such that the distance between these two connectors is set to a predetermined distance (to align precisely with the backplane board). The mechanical device used to maintain a predetermined distance between the two connectors of the assembly may comprise a U-shaped member, the upper part of this member being strategically inserted between these connectors.

Abstract: Methods are provided for the manufacture of a conductive layer on an insulating layer and for the manufacture of a built-up circuit board, each include an innovative step of irradiating the surface of an insulating (resin) layer with ultraviolet light, so that a conventional swelling process can be eliminated or simplified.

Abstract: The present invention features double- or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. The inventive process also provides a method of selectively etching germanium-containing gate conductor materials without significantly etching the adjacent silicon channel material. In this manner, the gate conductor can be encased in a dielectric shell without changing the length of the silicon channel. A single-crystal silicon wafer is utilized as the channel material. Pillars or stacks of self aligned dual gate MOSFETs are generated by etching, via the juxtaposition of overlapping germanium-containing gate conductor regions. Vertically etching through regions of both gate conducting material and dielectric insulating material provides an essentially perfect, self-aligned dual gate stack. A process is described wherein the gate conductor material can be selectively etched without etching the channel material.

Abstract: A method of mounting a component on a substrate includes applying a conductive adhesive on a contact pad joined to a substrate, aligning a component with the substrate such that at least one lead of the component is juxtaposed with the conductive adhesive, performing a partial cure of the conductive adhesive, testing performance of the component, and performing a full cure of the conductive adhesive. Another method includes the additional steps of applying a tacky film to the substrate and juxtaposing the component with the tacky film. When the testing in either embodiment shows a defective or misaligned component, the component may be replaced or repositioned by cold separation of the at least one component lead from the partially cured conductive adhesive. Optionally, additional conductive adhesive may be applied, when needed, before replacement or repositioning of a component.

Abstract: A method of mounting a component on a substrate includes applying a conductive adhesive on a contact pad joined to a substrate, aligning a component with the substrate such that at least one lead of the component is juxtaposed with the conductive adhesive, performing a partial cure of the conductive adhesive, testing performance of the component, and performing a full cure of the conductive adhesive. Another method includes the additional steps of applying a tacky film to the substrate and juxtaposing the component with the tacky film. When the testing in either embodiment shows a defective or misaligned component, the component may be replaced or repositioned by cold separation of the at least one component lead from the partially cured conductive adhesive. Optionally, additional conductive adhesive may be applied, when needed, before replacement or repositioning of a component.