Abstract: A chip carrier package that includes a cover plate attached to the stiffener by a reflowable bonding material is disclosed. Additionally, a thermally and electrically conductive bonding material between the cover plate and the chip itself may be included. Also a chip package including an alignment device to aid in properly aligning the cover plate on the stiffener. Furthermore, a method of packaging a chip including providing a reflowable material between the cover plate and stiffener body for attaching the cover plate to the stiffener, and simultaneously attaching the cover plate to the stiffener with an attaching of the carrier to an electronic circuit board.

Abstract: A printed wiring board comprises an insulating layer having a plurality of recesses formed along a predetermined edge portion of the insulating layer to extend through a side surface of the insulating layer, tabs for establishing electrical connection with an external electronic apparatus and which are formed on a surface of the insulating layer along the predetermined edge portion in correspondence with the plurality of recesses, and extensions connected electrically to the respective tabs and extending into the respective recesses. The printed wiring board may further comprise a plurality of dummy pads which are buried under the insulating layer in correspondence with the tabs and the extensions and which are electrically insulated from each other. The extensions are joined to the dummy pads through the recesses. The resulting board comprises a structure in which tabs are not easily peeled from an insulating layer.

Abstract: An electronic structure, and associated method of fabrication, for coupling a heat spreader above a chip to a chip carrier below the chip. Initially provided is a substrate, a chip on a surface of the substrate and coupled to the substrate, and the heat spreader. Then a fillet of at least one adhesive material is formed on the chip and around a periphery of the chip. Additionally, the heat spreader is placed on a portion of the fillet and over a top surface of the chip. The fillet couples the heat spreader to the substrate. An outer surface of the fillet makes a to contact angle of about 25 degrees with the surface of the substrate. The small contact angle not exceeding about 25 degrees prevents cracking of the substrate that would otherwise result from thermal cycling.

Abstract: A method of forming BGA interconnections having improved fatigue life is disclosed. In particular, a combination of mask-defined and pad-defined solder joints are selectively positioned within the BGA package. The mask-defined solder joints possess a high equilibrium height, which forces the pad-defined solder joints to elongate, thereby making the pad-defined solder joints more compliant. Further, the pad-defined solder joints possess a slightly longer fatigue life because the stress concentrations found in the mask-defined solder joints are not present in the pad-defined solder joints. Therefore, the fatigue life of BGA packages is increased by implementing a majority of mask-defined solder joints to maintain a high equilibrium height, and selectively placing pad-defined solder joints in high stress areas of the BGA package.

Abstract: An electrical structure or package, and associated method of formation. A plurality of logic chips is coupled electrically to a memory chip either through conductive members (e.g., solder balls) that interface with the memory chip and each logic chip, or through a sequential logic-to-memory electrically conductive path that includes: a first conductive member electrically coupled to a logic chip; an electrically conductive via path through a circuitized substrate; and a second conductive member electrically coupled to the memory chip. The logic chips are electrically coupled to the substrate either directly through an interfacing solder interconnection from the logic chip to the substrate, or indirectly through the memory chip such that the memory chip is electrically coupled to the substrate by an interfacing solder interconnect. The electrical structure may be plugged into a socket of a backplane of a circuit card.

Abstract: A method and apparatus for automated testing of a plurality of electrostatic discharge (ESD) devices on a wafer. The wafer has M padsets and N conductive pads on each padset, where m is at least 1, and n is at least 2, and each ESD device is conductively coupled to a unique plurality of pads of a padset of the M padsets. Testing sequences, under program control of a computer system, implement the testing of the ESD devices.

Abstract: A method of forming an electronic structure, including adhesively coupling a plated metallic layer (e.g. a copper layer) of a plated through hole (PTH) to holefill material (e.g., epoxy resin) distributed within the PTH. The adhesive coupling utilizes an adhesion promoter film on the plated metallic layer such that the adhesion promoter film is bonded to the resin. The adhesion promoter film may include a metallic oxide layer such as a layer containing cupric oxide and cuprous oxide, which could be formed from bathing a PTH plated with copper in a solution of sodium chlorite. The adhesion promoter film may alternatively include an organometallic layer such as a layer that includes a chemical complex of metal and an organic corrosion inhibitor. The organometallic layer could be formed from bathing the PTH in a bath of hydrogen peroxide, sulfuric acid, and the organic corrosion inhibitor.

Abstract: An organic integrated circuit chip carrier for high density integrated circuit chip attach, wherein the contact pads or microvias which provide electrical interconnections to external circuitry are located in a first array pattern, while the plated through holes or through-vias are located in a second array pattern. This allows utilization of wiring channels within the chip carrier in which signal wiring traces can be routed.

Abstract: A method and structure for conductively coupling a metallic stiffener to a chip carrier. A substrate has a conductive pad on its surface and an adhesive layer is formed on the substrate surface. The metallic stiffener is placed on the adhesive layer, wherein the adhesive layer mechanically couples the stiffener to the substrate surface and electrically couples the stiffener to the pad. The adhesive layer is then cured such as by pressurization at elevated temperature. Embodiments of the present invention form the adhesive layer by forming an electrically conductive contact on the pad and setting a dry adhesive on the substrate, such that the electrically conductive contact is within a hole in the dry adhesive. The electrically conductive contact electrically couples the stiffener to the pad. The curing step includes curing both the dry adhesive and the electrically conductive contact, resulting in the dry adhesive adhesively coupling the stiffener to the substrate.

Abstract: Apertures in a circuit board or chip carrier are filled with a cured photosensitive dielectric material by substantially filling the apertures in the circuit board or chip carrier and applying a layer of a thickness to the circuit board or chip carrier with a positive photosensitive dielectric material, exposing the photosensitive dielectric material to actinic radiation in such a way as to leave material located in apertures unexposed to the radiation; baking the structure so as to harden the unexposed photosensitive dielectric material and developing the exposed dielectric material in order to remove it leaving behind cured photosensitive dielectric material in the apertures.

Abstract: A semiconductor device having a thermoset-containing, dielectric material and methods for fabricating the same is provided. The device may take the form of a printed circuit board, an integrated circuit chip carrier, or the like. The dielectric material is a non-fibrillated, fluoropolymer matrix that has inorganic particles distributed therein and is impregnated with a thermoset material.

Abstract: A method for temporarily attaching an electrical component to a pad, testing the component, removing and replacing the component if necessary, and making a final attachment of the component to the pad. The method provides for attachment and removal of components, to and from pads located on the substrate of a printed circuit board, wherein the method enables components to be easily removed prior to final assembly without damaging the circuit board or components mounted thereon. The method utilizes a layer of conductive, radiation-curable adhesive placed between the component's lead and the pad. Radiation is then directed through a mask onto a portion of the adhesive layer, which cures the portion while leaving a remaining area of the adhesive layer uncured.

Abstract: Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.

Abstract: Providing a layer of ZnCr intermediate a dielectric substrate and a heat spreader enhances the adhesion between the dielectric substrate and heat spreader.

Abstract: An optical fiber guide includes a matrix of holes integrated directly into a substrate on which one or more optical chips are mounted. The substrate therefore functions both as a guide for optically coupling a plurality of optical fibers to an optical chip, as well as a carrier for the optical chip itself. The size of the fiber guide and its integration density is therefore improved over conventional fiber connectors. The substrate is preferably made of a material having a coefficient of thermal expansion substantially similar to the coefficient of thermal expansion of the optical chip. This ensures that the optical fibers will remain optically coupled to the chip through the matrix of holes in the substrate regardless of external temperature influences. If desired, integrated circuits may be mounted onto the substrate to increase the functionality of the fiber guide.

Abstract: A flexible chip carrier with contact pads on its upper surface matching those of the chip with said pads conductively connected to land grid array (LGA) pads on its lower surface matching the those of a card or PCB. The chip carrier is provided with a stiffening layer at the LGA interface. The stiffening layer is mechanically attached to the lower surface of the chip carrier. Holes are formed in the stiffening layer to expose the LGA pads. The holes are then filled with a conductive adhesive material. Compliant LGA bumps are applied to the uncured conductive adhesive material which material is then cured.

Abstract: A method and structure for reducing chip carrier flexing during thermal cycling. A semiconductor chip is coupled to a stiff chip carrier (i.e., a chip carrier having an elastic modulus of at least about 3×105 psi), and there is no stiffener ring on a periphery of the chip carrier. Without the stiffener ring, the chip carrier is able to undergo natural flexing (in contrast with constrained flexing) in response to a temperature change that induces thermal strains due to a mismatch in coefficient of thermal expansion between the chip and the chip carrier. If the temperature at the chip carrier changes from room temperature to a temperature of about −40° C., a maximum thermally induced displacement of a surface of the chip carrier is at least about 25% less if the stiffener ring is absent than if the stiffener ring is present.

Abstract: A parallel capacitor structure capable of forming an internal part of a larger circuit board or the like structure to provide capacitance therefore. Alternatively, the capacitor may be used as an interconnector to interconnect two different electronic components (e.g., chip carriers, circuit boards, and even semiconductor chips) while still providing desired levels of capacitance for one or more of said components. The capacitor includes at least one internal conductive layer, two additional conductor layers added on opposite sides of the internal conductor, and inorganic dielectric material (preferably an oxide layer on the second conductor layer's outer surfaces or a suitable dielectric material such as barium titanate applied to the second conductor layers). Further, the capacitor includes outer conductor layers atop the inorganic dielectric material, thus forming a parallel capacitor between the internal and added conductive layers and the outer conductors.

Abstract: A method and structure for forming a metalized blind via. A dielectric layer is formed on a metallic layer, followed by laser drilling a depression in the dielectric layer such that a carbon film that includes the carbon is formed on a sidewall of the depression. If the laser drilling does not expose the metallic layer, then an anisotropic plasma etching, such as a reactive ion etching (RIE), may be used to clean and expose a surface of the metallic layer. The dielectric layer comprises a dielectric material having a carbon based polymeric material, such as a permanent photoresist, a polyimide, and advanced solder mask (ASM). The metallic layer includes a metallic material, such as copper, aluminum, and gold. The carbon film is in conductive contact with the metallic layer, and the carbon film is sufficiently conductive to permit electroplating a continuous layer of metal (e.g., copper) directly on the carbon film without need of an electrolessly plated layer underneath the electroplated layer.

Abstract: A multi-layer circuit board is disclosed. The circuit board comprises a plurality of conductive planes; a plurality of plated through hole sets, each set comprising one or more plated through holes, none to all of the plated through holes of each set contacting at least one the conductive plane; a thermal break formed around each plated through hole in each conductive plane to which the plated through hole is connected; and one or more thermal vents, in the vicinity of each plated through hole in each conductive plane to which the plated through hole is connected. Additionally, surface mount technology pads are provided on a top surface of the circuit board.