Patents Represented by Attorney, Agent or Law Firm Leah Sherry
  • Patent number: 7072851
    Abstract: A credit card incentive program wherein a credit card issuer issues a credit card to a credit card holder, who has an outstanding installment loan account with a lending institution; wherein the credit card holder can earn a periodic rebate through use of the credit card, which rebate is in the form of a payment to the lending institution made by the credit card issuer on behalf of the credit card holder; and wherein the payment is applied against the outstanding principal on the installment loan account.
    Type: Grant
    Filed: April 16, 1999
    Date of Patent: July 4, 2006
    Assignee: Bank of America Corporation
    Inventors: Warren S. Wilcox, Edmond I. Eger
  • Patent number: 6631131
    Abstract: A biased arbitration technique utilizes a transpose table to arbitrate access to a shared resource. Each column of transpose table is a binary bias vector encoding a bias value assigned to one of the requestors. The rows of the table are fetched to assure that requestors having high bias values are granted more frequent access to the shared resource. A look-ahead feature skips rows having all zeros and an unbiased cycle that assures all requesting ports are serviced regardless of their bias values.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: October 7, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: David P. Sonnier, William J. Watson, Robert B. Mizell, Robert W. Horst
  • Patent number: 6622247
    Abstract: A computerized method is provided for certifying a digital object. The digital object is uniquely identified with an identification. The identification is registered with a certification authority using a first public/private key exchange to receive a certificate of the digital object. Authenticity of the object is addressed by means of certification of the supplier's identity, in conjunction with integrity validation of the object. The digital object is tested to receive a compliance label using a second public/private key information exchange. The digital object is then distributed along with the certificate, and the label using a third public/private key information exchange. Ongoing confidence in object compliance is sustained by re-affirmation and/or notification mechanisms.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: September 16, 2003
    Assignee: Hewlett-Packard Development Company, LP
    Inventor: James DeWitt Isaak
  • Patent number: 6603414
    Abstract: Groups of characters, including alpha, numeric, or other symbols, are represented in a binary form by one or more first or second code representations for each character. The first code representation will have a value indicative of a predetermined number of second code representations, wherein each of the second code representations identify a corresponding one of the characters.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: August 5, 2003
    Assignee: Compaq Computer Corporation
    Inventor: L. John Postas
  • Patent number: 6571111
    Abstract: In a compunctions network of low power devices, power consumption of the devices is reduced by periodically receiving a timing signal in each device from a transmitter external to the network. A real-time clock in each of the devices is synchronized to the periodically received timing signal to determine a synchronized timing interval. Transmitting and receiving of data between the devices is initiated during an awake period of the synchronized timing interval. Power consumption is reduced in each of the devices during a sleep period of the synchronized timing interval, the sleep period being significantly longer than the awake period.
    Type: Grant
    Filed: August 5, 1998
    Date of Patent: May 27, 2003
    Assignee: Compaq Computer Corporation
    Inventors: Robert Nelson Mayo, William Riis Hamburgen
  • Patent number: 6559843
    Abstract: Volumetric data are rendered onto an image plane by first organizing the volumetric data into a plurality of blocks of data, each block of data including a plurality of voxels arranged in cubic structure. The blocks of volumetric data are stored in, and processed by a processor element array of a massively data-parallel computer system. For any viewing angle, a plurality of parallel rays are cast through the image plane to traverse the volumetric data. In a ray collection phase, each processor element, in parallel with the other processor elements, determines which segments of the rays interpolate voxels of its associated block of data. In a segment value combination phase, each processor element, in parallel with the other processor elements, determines the integrated contribution of the interpolated voxels on the path of the ray segments traversing its block of data.
    Type: Grant
    Filed: February 26, 1996
    Date of Patent: May 6, 2003
    Assignee: Compaq Computer Corporation
    Inventor: William M Hsu
  • Patent number: 6549930
    Abstract: A method is provided for scheduling execution of a plurality of threads executed in a multithreaded processor. Resource utilizations of each of the plurality of threads are measured while the plurality of threads are concurrently executing in the multithreaded processor. Each of the plurality of threads is scheduled according to the measured resource utilizations using a thread scheduler.
    Type: Grant
    Filed: November 26, 1997
    Date of Patent: April 15, 2003
    Assignee: Compaq Computer Corporation
    Inventors: George Z. Chrysos, Jeffrey A. Dean, James E. Hicks, Jr., Carl A. Waldspurger, William E. Weihl
  • Patent number: 6545981
    Abstract: A system and method for facilitating both in-order and out-of-order packet reception in a SAN includes requestor and responder nodes, coupled by a plurality of paths, that maintain the good and bad status of each path and also maintain local copies of a message sequence number. If an error occurs for a transaction over a given path, the requestor informs the responder, over a good path, that the given path has failed and both nodes update their path status to indicate that the given path is bad. A barrier transaction is used by the requestor to determine whether the error is transient or permanent, and, if the error is transient, the requestor retries the transaction.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: April 8, 2003
    Assignee: Compaq Computer Corporation
    Inventors: David J. Garcia, Richard O. Larson, Stephen G. Low, William J. Watson
  • Patent number: 6539414
    Abstract: Incorporation of a collateral process as a participant in a transaction is made possible by a method and system in accordance with the present invention. Typically, after the transaction is initiated, the collateral process is called and then is registered as a participant,in the transaction. A prepare signal is sent to each registered collateral process when end stage of the transaction is reached. Then, a ready signal is received from the collateral process if the collateral process is completed successfully; and an abort signal is received from the collateral process if the collateral process does not complete successfully or a violation is detected. If a ready signal is received, a commit record is written to a log, and a commit signal is sent to each registered collateral process. In response to the commit signal, a forgotten signal is received from each registered collateral process.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: March 25, 2003
    Assignee: Compaq Computer Corporation
    Inventors: Johannes Klein, Albert C. Gondi, Sitaram V. Lanka, William J. Carley
  • Patent number: 6535904
    Abstract: A protocol for a transaction involving two homogeneous or two heterogeneous computing systems involves starting a transaction on one of the two systems, sending a request for participation in the transaction to an application resident on the other of the two systems, together with an identification and address of the transaction. Upon receipt of the request, the application will initiate a subordinate transaction through a resident (subordinate) transaction manager. The subordinate transaction manager will notify the Beginner transaction manager and at the same time cause the application to start work on the request. Later, the subordinate transaction, through the subordinate transaction manager participates in a two-phase commit protocol that concludes the transaction to ensure that all changes effected by the transaction are done, or none are done, i.e., the transaction is aborted.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: March 18, 2003
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Johannes Klein, Keith B. Evans, Albert C. Gondi, Sitaram V. Lanka, Roger J. Hansen
  • Patent number: 6516032
    Abstract: An encoder accepts an N byte set of values for each of a plurality of image components, with N being greater than one and, for each N byte set of values, identifies a compressed symbol length, K, wherein K is the smallest integer such that the difference between any two adjacent bytes is expressible in K bits or less, outputs an indication of K and outputs a K bit difference between the byte and an immediately prior byte, for each byte in the set.
    Type: Grant
    Filed: March 8, 1999
    Date of Patent: February 4, 2003
    Assignee: Compaq Computer Corporation
    Inventors: Alan Heirich, Pankaj Mehra, Robert W. Horst
  • Patent number: 6496825
    Abstract: Systems and Methods for identifying in the gateway processes or application processes whether an imported transaction is a loop-back transaction, and if so performing work for the imported transaction under the parent transaction. Upon receiving a work request from a remote transaction processing system, an endpoint identifier included as part of the work request is analyzed to determine whether the work request is associated with a parent transaction initiated at the local transaction processing system. If the endpoint identifier indicates that the work request is associated with a transaction initiated in the local transaction processing system, a global transaction identifier included as part of the work request is analyzed to determine the identity of the parent transaction. If the work request includes a remote TIP URL, the application process that receives the request is configured to analyze the global transaction identifier and determine the identity of the parent transaction.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: December 17, 2002
    Assignee: Compaq Computer Corporation
    Inventors: Johannes Klein, Roger J. Hansen, Sitaram V. Lanka, Albert C. Gondi
  • Patent number: 6496940
    Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: December 17, 2002
    Assignee: Compaq Computer Corporation
    Inventors: Robert W. Horst, David J. Garcia
  • Patent number: 6480502
    Abstract: A method for broadcasting packets in a network that includes a plurality of switches. The network can logically be represented by a spanning tree plus cross-links. In order to avoid deadlock during a broadcast, a broadcast packet is sent from an originating switch to a root switch of the network, and a copy of the packet is sent from a current switch to all descendant switches when all copies of the packet have been received in the current switch.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: November 12, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Martin Abadi, Thomas Lee Rodeheffer
  • Patent number: 6473525
    Abstract: A method for detecting an image edge within a dithered image. A pixel within a support region is selected for processing. The differences between pixel values in the region and the selected pixel are computed to form a current difference map. Whether the selected pixel in the region differ by no more than one resolution level from any other pixel of the region is determined from the current difference map. An edge is determined not to exist within the region if the difference map for a region contains no values differing by more than one resolution level. An edge is determined to exist within a region if the difference map for the selected pixel and region contain values differing by more than one resolution level. Alternatively, a difference map for the selected region of support is determined and compared to a table of all possible valid difference maps. If a corresponding difference map is found within the table then an edge does not exist within the presently processed region of support.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: October 29, 2002
    Assignee: Compaq Computer Corporation
    Inventors: Shiufun Cheung, Robert A. Ulichney, Robert MacNamara, Giridharan Iyengar
  • Patent number: 6470398
    Abstract: A computing environment (2) includes multiple CPUs (5a-c), multiple nonshared memory spaces and a means for implementing a select system call (10a-c).
    Type: Grant
    Filed: April 7, 1997
    Date of Patent: October 22, 2002
    Assignee: Compaq Computer Corporation
    Inventors: Bahman Zargham, Jim Uren, Robert Shaw, Sylvia Chan, Lars Plum, Minoo Gupta
  • Patent number: 6470342
    Abstract: Systems and methods for supporting and maintaining a distributed global map of transaction identifiers at the gateway processes using a hashing algorithm configured on each application process to access the global maps. A global map of transaction identifiers that associates global transaction identifiers with remote local transaction identifiers is maintained at each gateway process. When an application process performing work for a particular transaction desires to export the transaction to a remote node, a hashing function configured on the application process is applied to the global transaction identifier associated with the particular transaction. Application of the hashing function to the global transaction identifier identifies one of the gateway processes. The global transaction identifier is stored to the global map associated with that gateway process.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: October 22, 2002
    Assignee: Compaq Computer Corporation
    Inventors: Albert C. Gondi, Johannes Klein, Sitaram V. Lanka, Roger J. Hansen, Sameer Joshi
  • Patent number: 6457125
    Abstract: Method and apparatus is provided for securely configuring a programmable hardware device from a remote source. The programmable hardware device includes a plurality of programmable logic modules. A host receives configuration information from the remote source, where the configuration information defines a function of the programmable logic modules. The host encrypts the configuration information according to a cryptographic algorithm. The encrypted information is transferred to a special download engine at the programmable hardware device, which decrypts the information according to the same cryptographic algorithm. The programmable logic modules are thus configured by the decrypted configuration information, which has been securely downloaded from the remote source.
    Type: Grant
    Filed: December 14, 1998
    Date of Patent: September 24, 2002
    Assignee: Compaq Computer Corporation
    Inventors: Donald P. Matthews, Jr., Ralph R. Bestock
  • Patent number: 6453406
    Abstract: In a data processing system of the type having multiple processor units coupled to one another by a bus means for interprocessor communications there is provided a fiber optic interconnection system to interconnect the bus means of multiple processor sections to one another, thereby allowing groups of the processor units to be physically spaced from one another. The fiber optic interconnect system includes, for each multiprocessor unit section functions to receive messages communicated on the interprocessor bus of that section for receipt by a destination processor of the other section, format the message for fiber optic transmission, and transmit the message; and circuitry for receiving messages on the fiber optic link, scheduling the message for transmission to the destination processor, and maintaining that scheduling in the face of receipt of another message for the same processor unit.
    Type: Grant
    Filed: December 13, 1993
    Date of Patent: September 17, 2002
    Assignee: Compaq Computer Corporation
    Inventors: Scott Sarnikowski, Unmesh Agarwala, Stanley S. Quan, Charles E. Comstock, Frank G. Moore
  • Patent number: D499398
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: December 7, 2004
    Assignee: Allied Telesis Kabushiki Kaisha
    Inventors: Takumi Nagai, Hiroyuki Tomino