Abstract: In a multiple processing system or cluster, a pair of processes, assuming the role of a primary process and a backup process to the primary process, are replaced on-line by stopping the backup process; creating the replacement backup process; checking to ensure compatibility between the primary and replacement backup processes so that communication between them is possible and information sent by the primary process to the replacement will be correctly received and handled; providing the replacement backup process with that state of the primary process needed in order to take over the function and operation of the primary process; switching roles so that the replacement backup process now takes over the function and operation of the primary, and the primary becomes the backup; and repeating the steps of creating, checking, providing and switching, to conclude with a newly-installed replacement primary process and a replacement backup process, completing the on-line replacement of the process pair.

Abstract: A method schedules execution contexts in a computer system based on memory interactions. The computer system includes a processor and a hierarchical memory arranged in a plurality of levels. Memory transactions are randomly sampled for a plurality of contexts. The contexts can be threads, processes, or hardware contexts. Resource interactions of the plurality of contexts is estimated, and particular contexts are chosen to be scheduled based on the estimated resource interactions.

Abstract: A biased arbitration technique utilizes a transpose table to arbitrate access to a shared resource. Each column of transpose table is a binary bias vector encoding a bias value assigned to one of the requesters. The rows of the table are fetched to assure that requesters having high bias values are granted more frequent access to the shared resource.

Abstract: A system and method that implement a strategy for automatically generating self-checking tests of source-to-source translation. The tests make certain that software components produced by a source-to-source computer language translator continue to be binary-compatible with all other software components with which they previously interacted correctly, including components that remain in the original programming language. To that end, the correctness of procedure interfaces in a target computer program is also verified. With this strategy, correct translation of text preprocessor mechanisms such as macros, conditionally compiled regions of code, and source file inclusion can be achieved. The target program is the result of translating a source program written in a different language from the target program. The system creates a set of procedure calls to each procedure in the source program. The system also creates a set of callable procedures with the same interface specification as in the source program.

Abstract: A protocol for a transaction involving two homogeneous or two heterogeneous computing systems involves starting a transaction on one of the two systems, sending a request for participation in the transaction to an application resident on the other of the two systems, together with an identification and address of the transaction. Upon receipt of the request, the application will initiate a subordinate transaction through a resident (subordinate) transaction manager. The subordinate transaction manager will notify the Beginner transaction manager and at the same time cause the application to start work on the request. Later, the subordinate transaction, through the subordinate transaction manager participates in a two-phase commit protocol that concludes the transaction to ensure that all changes effected by the transaction are done, or none are done, i.e., the transaction is aborted.

Abstract: A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip.

Abstract: A logical processor is formed from a pair of processor units operating in close synchrony to perform self-check operations. Outputs of one of the processor units are compared to that of the other processor unit. When one of the processor units experiences an error, creating a divergence, that error and/or divergence will be made known to the Master processor which will then determine if recovery from the error can be made and, if so, save its processing state to memory, cause a reset of both processor units to an initial state to begin executing reinitialization code using the prior saved state for both processor units.

Abstract: A system and method for scheduling packets between multiple links of an adaptive set utilizes a destination register or a cache line associated with each of the alternate links of the network switch. Each of the cache lines holds the destination of the last packet that used the link. Upon arrival, a packet associatively checks the content of all cache lines. If it hits, then it uses the corresponding link; otherwise, the packet is scheduled according to a round-robin policy or other default policy.

Abstract: A cryptographic system and method for encrypting and decrypting data using public key cryptography. The encryption and decryption may be divided into tasks that may operate in parallel. A secure method of initializing the cryptographic system to allow for secure operations and protect against tampering with application software. The application program is retrieved from an encrypted file in external memory and authenticated before being executed.

Abstract: A method for sampling the performance of a computer system is provided. The computer system includes a plurality of functional units. The method selects transactions to be processed by a particular functional unit of the computer system. State information is stored while the selected transactions are processed by the functional unit. The state information is analyzed to guide optimization.

Abstract: The invention provides a method for acquiring a lock in a network of processors with globally ordered remote-writes. A process requesting a lock changes an associated ticket number from zero to one. Next, the process determines if every other process attempting to acquire the lock has a ticket number of zero. If true, the request for the lock is immediately granted. Otherwise, if false, the process changes its ticket number to a value greater than that of every other process, and the process waits until its ticket number is the lowest non-zero ticket number, in which case the lock is granted with mutual exclusion.

Abstract: A method and apparatus for presenting the multiple processors of a cluster as a single virtual host to a network wherein the processors are communicatively coupled among themselves and to a network interface. The network interface is communicatively coupled to the network. One of the processors is designated a primary parallel I/O processor. One address is advertised on said network for said multiple processors, and filter trees in the network interface direct the interface to forward packets from the network addressed to that address to the primary parallel I/O processor. Later, the filter tree is modified to direct the network interface to forward a specific subset of the packets directly to a particular processor.

Abstract: A multi-user bus is divided into a number of bus portions, one for each user. Each bus portion is coupled, at one end, to one of the multiple users and through an impedance matching network to the other bus portions in a star configuration. The disclosed embodiment teaches various resistive impedance matching networks.

Abstract: A system for preventing a powered-up sub-unit from driving a powered-off low-impedance load transitions to a NO_CLOCK state and tri-states output drivers of the sub-unit output unless a clock signal is received from a connected sub-unit. While in the NO_CLOCK state, the sub-unit periodically transmits bursts of clock signals to signal the other sub-unit that it is powered up.

Abstract: A symmetrical processing system includes a number of processor units sharing a memory element. At least a portion of the memory element is partitioned so that separate memory partitions are made exclusively available to some if not all the processor units.

Abstract: A system for timing intervals in a computer. The system provides an interval timing service for processes running in a computer system. The timing service supports a potentially large number of interval timers by using “timing wheels” that “turn” at different periods. The time base for the fastest turning wheel can be an interrupt event or some other hardware or software control.

Abstract: A method and apparatus for sorting and classifying communications frames received over a network prior to delivery, using a collection of filters arranged as a decision-making tree with destinations for the frames as the leaves of the tree.

Abstract: A monitor function is implemented to monitor and control service processes and other system entities that perform tasks on a distributed network. The monitor function tracks the demise and instantiation of processes and entities that either export or import instrumentation. Any service process or other system entity (driver, interrupt handler, system library procedure) can export instruments (indicators, controls, testpoints). Instrument updates are propagated automatically if they are significant. The importing process conveys the information to a management system so that a human operator, or automated system, can observe and control the operation of the network service. One aspect of the invention uses a backup exporter to take over the processing of an exporter that has become nonfunctional. Another aspect of the invention determines when a CPU has gone down and acts accordingly to identify service processes that were associated with an exporter in the down CPU.

Abstract: An image generator computes a set of light sample points, wherein each light sample point is a point on a light source from a geometric model, and an irradiance image is computed for each light sample point, wherein an irradiance image is a view-dependent image taken with the light sample point being the view point and the light source for the irradiance image. From the irradiance images, the image generator creates an irradiance texture for each object in a set of objects being considered the scene and the image generator renders the image of the objects in the set of objects with each object's coloring determined, at least in part, from the object's irradiance texture. Depending on performance requirements, one or more operation of the image generator is parallelized.

Abstract: A method for inverse dithering a dithered image using a filter selected from a set of filters arranged in a preselected order is disclosed. Upon receipt of a selected portion of a dithered image, the selected portion is up-multiplied from a first amplitude resolution to a second amplitude resolution. The up-multiplied dithered image at the second amplitude resolution is then filtered by the selected filter coefficients to generate the inverse dithered image.