Patents Represented by Attorney Leffert Jay & Polglaze, P.A.

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  • Compensation of back pattern effect in a memory device
    Patent number: 7936606
    Abstract: In one or more of provided embodiments, a read operation is compensated for back pattern effect. A bit line current is generated by a read operation that biases the word lines. As part of a back pattern effect measurement phase, at predetermined time intervals an indication of the discharge status of the bit line is stored in a latch of a set of N latches coupled to each bit line. At the end of the measurement phase, the set of latches contains a multiple bit word that is an indication of the back pattern effect experienced by that particular series string of memory cells. This back pattern effect indication is used in subsequent read operations to adjust the timing of the operation.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: May 3, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Tommaso Vali, Violante Moschiano, Giovanni Santin
  • Memory device operation
    Patent number: 7936608
    Abstract: Non-volatile memory devices utilizing a modified NAND architecture where ends of the NAND string of memory cells are selectively coupled to different bit lines may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of the memory cells can be accomplished in the same manner as a traditional NAND memory array. However, reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device or by using one bit line as a ground node for sensing current flow through the strings. The use of bit lines for virtual grounding is further suitable to other array architectures.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: May 3, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Error detection and correction scheme for a memory device
    Patent number: 7930612
    Abstract: Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are operated in parallel to determine if the data word has any errors. The results of the parallel detection operations are communicated to a controller circuit. If an error is present that can be corrected by the Hamming code correction operation, this is performed and the Reed-Solomon code detection operation is performed on the corrected word. If the error is uncorrectable by the Hamming code, the Reed-Solomon code correction operation is performed on the word.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: April 19, 2011
    Assignee: Micron Technology, Inc.
    Inventors: William H. Radke, Shuba Swaminathan, Brady L. Keays
  • Programming method to reduce word line to word line breakdown for NAND flash
    Patent number: 7924619
    Abstract: A NAND architecture non-volatile memory device and programming process programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines adjacent to the selected word line and memory cell being programmed in order to reduce voltage differences between the word lines of the memory cell string or array during a programming cycle. This allows the word line to word line voltage differential to be reduced and thus decreases the likelihood of breakdown or punch through of the insulator materials placed between the adjacent word lines.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: April 12, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Seiichi Aritome
  • Selective threshold voltage verification and compaction
    Patent number: 7924617
    Abstract: Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of threshold voltages in memory devices utilizing a NAND architecture. By providing for compaction verification and/or compaction on less than all word lines of a NAND string, increased tightening of the distribution may be achieved over prior methods performed concurrently on all word lines of a NAND string.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: April 12, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • NROM flash memory devices on ultrathin silicon
    Patent number: 7915669
    Abstract: An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: March 29, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Programming based on controller performance requirements
    Patent number: 7916536
    Abstract: Methods and solid state drives are disclosed, including a solid state drive that is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits). Programming of the solid state drive, having an array of non-volatile memory cells, might include adjusting the level of each memory cell being programmed in response to a desired performance level of a controller circuit.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: March 29, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
  • Methods for programming a memory device and memory devices using inhibit voltages that are less than a supply voltage
    Patent number: 7916546
    Abstract: Methods for programming a memory array and memory devices are disclosed. In one such method, inhibited bit lines are charged to an inhibit voltage that is less than a supply voltage. The word lines of memory cells to be programmed are biased at a programming preparation voltage that is less than a nominal programming preparation voltage as used in the conventional art. Programming pulses can be applied to selected word lines of the memory cells to be programmed when the uninhibited bit lines are at 0V.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: March 29, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Shigekazu Yamada
  • Method for reading a multilevel cell in a non-volatile memory device
    Patent number: 7917685
    Abstract: A non-volatile memory device has a memory array comprising a plurality of memory cells. The array can operate in either a multilevel cell or single level cell mode and each cell has a lower page and an upper page of data. The memory device has a data latch for storing flag data and a cache latch coupled to the data latch. A read method comprises initiating a lower page read of a memory cell and reading, from the data latch, flag data that indicates whether a lower page read operation is necessary.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: March 29, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Chang Wan Ha
  • Memory system for data storage and retrieval
    Patent number: 7917709
    Abstract: According to a first aspect of an embodiment of the invention, there is provided a method of data storage and retrieval for use in a solid state memory system, having a non-volatile memory, wherein data is written to the non-volatile memory in the form of at least one logical sector the method comprising: monitoring the logical sector data which is to be written to the non-volatile memory, detecting the presence of a pattern in the logical sector data, upon detecting a repetitive pattern recording the repetitive pattern of the logical sector in a sector address table in the non-volatile memory without making a record of the logical sector data in the nonvolatile memory.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: March 29, 2011
    Assignee: Lexar Media, Inc.
    Inventor: Sergey Anatolievich Gorobets
  • NAND interface
    Patent number: 7916557
    Abstract: A NAND interface having a reduced pin count configuration, in which all command and address functions and operations of the NAND are provided serially on a single serial command and address pin adapted to receive all commands and addresses, and data communication is performed on a number of data communication pins.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: March 29, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Ebrahim Abedifard
  • Multi-state memory cell with asymmetric charge trapping
    Patent number: 7911837
    Abstract: A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide-nitride-oxide structure. An asymmetrical bias on the drain/source areas causes the drain/source area with the higher voltage to inject an asymmetric distribution hole by gate induced drain leakage injection into the trapping layer substantially adjacent that drain/source area.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: March 22, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Kirk Prall
  • Temperature compensation of memory signals using digital signals
    Patent number: 7911865
    Abstract: A temperature sensor generates a digital representation of the temperature of the integrated circuit. A logic circuit reads the digital temperature and generates a multiple bit digital representation of an operational voltage and a multiple bit digital representation of a timing signal, both being functions of the integrated circuit temperature. A voltage generator converts the digital representation of the operational voltage to an analog voltage that biases portions of the integrated circuit requiring temperature compensated voltages. In one embodiment, the temperature compensated voltages bias memory cells. A timing generator converts the multiple bit digital representation of the timing signal to a logic signal.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: March 22, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Michele Incarnati, Giovanni Santin
  • Non-volatile memory device having assignable network identification
    Patent number: 7913033
    Abstract: Memory devices and methods disclosed such as memory devices that include a network identification that uniquely identifies the memory device on a network. The memory device can then receive memory commands that include the network identification. The memory device can also generate memory commands, including the network identification, for broadcast over the network.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: March 22, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Memory array with a pair of memory-cell strings to a single conductive pillar
    Patent number: 7906818
    Abstract: Memory arrays and methods of forming memory arrays are disclosed. One such memory array has a first string of serially-coupled first memory cells and a second string of serially-coupled second memory cells sharing a single conductive pillar which forms a channel for both strings of serially-coupled memory cells. For example, a first memory cell can have a first control gate on the first side of the conductive pillar and a first charge trap interposed between the first side of the conductive pillar and the first control gate. A second memory cell can have a second control gate on the second side of the conductive pillar and a second charge trap interposed between the second side of the conductive pillar and the second control gate. The first and second charge traps are electrically isolated from each other and the first and second control gates can be electrically isolated from each other.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: March 15, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Theodore T. Pekny
  • Moving sectors within a block of information in a flash memory mass storage architecture
    Patent number: 7908426
    Abstract: A device is disclosed for storing mapping information for mapping a logical block address identifying a block being accessed by a host to a physical block address, identifying a free area of nonvolatile memory, the block being selectively erasable and having one or more sectors that may be individually moved. The mapping information including a virtual physical block address for identifying an “original” location, within the nonvolatile memory, wherein a block is stored and a moved virtual physical block address for identifying a “moved” location, within the nonvolatile memory, wherein one or more sectors of the stored block are moved. The mapping information further including status information for use of the “original” physical block address and the “moved” physical block address and for providing information regarding “moved” sectors within the block being accessed.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: March 15, 2011
    Assignee: Lexar Media, Inc.
    Inventors: Petro Estakhri, Berhanu Iman, Ali Ganjuei, Joumana Fahim, legal representative
  • Memory device reference cell programming method and apparatus
    Patent number: 7907444
    Abstract: Memory devices and methods are disclosed, such as those facilitating an assignment scheme of reference cells throughout an array of memory cells. For example, one such assignment scheme assigns reference cells in a staggered pattern by row wherein each column contains a single reference cell. Additional schemes of multiple reference cells assigned in a repeating or a pseudo-random pattern are also disclosed.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: March 15, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Frankie F. Roohparvar
  • Sensing for memory read and program verify operations in a non-volatile memory device
    Patent number: 7903461
    Abstract: Methods for sensing in a memory device, a memory device, and a memory system are disclosed. In one such sensing method, a single read operation with multiple sense amplifier circuit comparisons to a reference threshold level are performed to determine a state of a selected memory cell. A ramped voltage turns on the selected memory cell when the ramped voltage reaches the threshold voltage to which the selected memory cell is programmed. In one embodiment, the turned on memory cell discharges its respective bit line.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: March 8, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Uday Chandrasekhar, Ebrahim Abedifard, Allahyar Vahidimowlavi
  • Memory array segmentation and methods
    Patent number: 7903464
    Abstract: An embodiment of a method includes applying a first voltage to a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed in a second well region of a second conductivity type, at least one target memory cell coupled to the selected word line and formed on one of the first well regions, the first well regions electrically isolated from each other; applying a second voltage to unselected word lines, each unselected word line commonly coupled to portions of a row of memory cells not targeted for programming and respectively formed on the first well regions; and applying a third voltage to those first well regions that do not include the at least one target memory cell.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: March 8, 2011
    Assignee: Micron Technologies, Inc.
    Inventor: Aaron Yip
  • Floating-gate memory cell and memory device and electronic system therewith
    Patent number: 7898017
    Abstract: A floating-gate memory cell has a tunnel dielectric layer that overlies a silicon-containing semiconductor substrate and that is adjacent a trench formed in the semiconductor substrate. A floating-gate layer, having at least one silicon-containing layer, overlies the tunnel dielectric layer. An intergate dielectric layer overlies the floating-gate layer, and a control gate layer overlies the intergate dielectric layer. A first silicon oxide layer is formed on an edge of the at least one silicon-containing layer of the floating-gate layer and extends across a first portion of an edge of the tunnel dielectric layer. A second silicon oxide layer is formed on a sidewall of the trench and extends across a second portion of the edge of the tunnel dielectric layer.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: March 1, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Garo Derderian, Nirmal Ramaswamy