Patents Represented by Attorney Leffert Jay & Polglaze, P.A.

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  • Syringe for biomaterial
    Patent number: 7972339
    Abstract: An injector device for percutaneously injecting biomaterial in the form of particles of different sizes or in the form of paste includes a trocar (12) of generally cylindrical shape presenting a open first end with a sharp edge, the wall of the first end presenting at least one orifice (36, 38) for passing the biomaterial, and a second end (42) that is likewise open; a reservoir (14) for receiving the biomaterial, the reservoir including a part (20) of substantially cylindrical shape having two open ends, the cylindrical part being capable of being inserted at least in a portion of the trocar via the second end thereof; removable plugs for closing both ends of the reservoir; and a piston (16) insertable in the cylindrical part when the plugs are removed, the piston being capable of sliding in the cylindrical part and in the first end of the trocar.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: July 5, 2011
    Assignee: Bio Holdings International Limited
    Inventors: Nasser Nassiri, Yves Cirotteau, Alberto Jussmann
  • Finned memory cells
    Patent number: 7968930
    Abstract: For an embodiment, a memory array has a plurality fins protruding from a substrate. A tunnel dielectric layer overlies the fins. A plurality floating gates overlie the tunnel dielectric layer, and the floating gates correspond one-to-one with the fins protruding from the substrate. An intergate dielectric layer overlies the floating gates. A control gate layer overlies the intergate dielectric layer. Each fin includes an upper surface rounded by isotropic etching.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: June 28, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Seiichi Aritome
  • Charge loss compensation methods and apparatus
    Patent number: 7969788
    Abstract: Methods and apparatus for compensating for charge loss in memories include tracking a specific block of the main memory array and determining charge loss compensation by comparing pre-cycled and post-cycled mean threshold voltages for the tracking block; or tracking each block of the main memory and determining charge loss and compensation on a block by block basis.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: June 28, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Daniel Elmhurst, Paul Ruby
  • Isolation regions
    Patent number: 7968425
    Abstract: Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first dielectric layer adjoining exposed substrate surfaces within the trench using a high-density plasma process, forming a layer of spin-on dielectric material on the first dielectric layer so as to fill a remaining portion of the trench, and densifying the layer of spin-on dielectric material.
    Type: Grant
    Filed: July 14, 2006
    Date of Patent: June 28, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Zailong Bian, Xiaolong Fang
  • Interconnecting bit lines in memory devices for multiplexing
    Patent number: 7968951
    Abstract: An embodiment of a memory device has a plurality of conductive plugs formed on a semiconductor substrate and a pair of successively adjacent first and second bit lines overlying and in contact with each of the conductive plugs.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: June 28, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Seiichi Aritome
  • Scalable high density non-volatile memory cells in a contactless memory array
    Patent number: 7964909
    Abstract: A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion area is formed in each mesa top and a trench diffusion area is formed under each trench. A vertical, non-volatile memory cell is formed on each sidewall of the trench. Each memory cell is comprised of a fixed threshold element located vertically between a pair of non-volatile gate insulator stacks. In one embodiment, each gate insulator stack is comprised of a tunnel insulator formed over the sidewall, a deep trapping layer, and a charge blocking layer. In another embodiment, an injector silicon rich nitride layer is formed between the deep trapping layer and the charge blocking layer.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: June 21, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Programming rate identification and control in a solid state memory
    Patent number: 7961518
    Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes determining a rate of programming (i.e., rate of movement of the respective threshold voltage) of the memory cells and biasing the corresponding bit line with a programming rate control voltage that is greater than the bit line enable voltage and less than the inhibit voltage. This voltage can be adjusted to change the speed of programming. A capacitor coupled to the bit line stores the programming rate control voltage in order to maintain the proper bit line bias for the duration of the programming operation or until it is desired to change the programming rate.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: June 14, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Program and read trim setting
    Patent number: 7961517
    Abstract: A method and apparatus for setting trim parameters in a memory device provides multiple trim settings that are assigned to portions of the memory device according to observed or tested programming speed and reliability.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: June 14, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Seiichi Aritome
  • Verifying an erase threshold in a memory device
    Patent number: 7957198
    Abstract: In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well is biased with the negative voltage and the erase verify operation is performed to determine the erased state of the cell(s).
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: June 7, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Method of programming memory cells of series strings of memory cells
    Patent number: 7957196
    Abstract: Method of programming memory cells of series strings of memory cells include programming a target memory cell of a series string of memory cells after programming each memory cell of the string located between the target memory cell and a first end of the string, and verifying the programming of the target memory cell by applying a bias at a second end of the string opposite the first end and sensing a voltage developed at the first end in response to the bias.
    Type: Grant
    Filed: July 2, 2010
    Date of Patent: June 7, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • Double-doped polysilicon floating gate
    Patent number: 7956402
    Abstract: The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method includes forming a first dielectric layer on a semiconductor substrate and forming a floating gate above the first dielectric layer, the floating gate comprised of a first layer doped with a first type of dopant material and a second layer doped with a second type of dopant material that is opposite the first type of dopant material in the first layer. The method further includes forming a second dielectric layer above the floating gate, forming a control gate above the second dielectric layer, and forming a source and a drain in the substrate.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: June 7, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Chun Chen, Kirk D. Prall
  • Method for programming a non-volatile memory device to reduce floating-gate-to-floating-gate coupling effect
    Patent number: 7952922
    Abstract: A method for programming a non-volatile memory array comprising a plurality of memory cells. Each cell is adapted to store a lower and an upper page of data. The method: programs the lower page of predetermined memory cells with first predetermined data and the upper page with second predetermined data. One of the lower page or the upper page of the predetermined memory cells is reprogrammed with the first or second predetermined data, respectively.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: May 31, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Seiichi Aritome
  • Storage capacity status
    Patent number: 7949822
    Abstract: In one embodiment of the present invention, a memory device is disclosed to include memory organized into blocks, each block having a status associated therewith and all of the blocks of the nonvolatile memory having collectively a capacity status associated therewith and a display for showing the capacity status even when no power is being applied to the display.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: May 24, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Petro Estakhri, Martin Ragnar Furuhjelm, Ngon Le, Jerrold Allen Beckmann, Neal Anthony Galbo, Steffen Markus Hellmold, Jarreth Romero Solomon
  • Pipelined burst memory access
    Patent number: 7949844
    Abstract: A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: May 24, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Giuliano Gennaro Imondi, Maurizio Di Zenzo, Mario Antonio Fazio
  • Erase block data splitting
    Patent number: 7944748
    Abstract: A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: May 17, 2011
    Assignee: Micron Technology, Inc.
    Inventors: David Eggleston, Anthony Moschopoulos, Michael Murray, Brady Keays
  • Erase verify in memory devices
    Patent number: 7944755
    Abstract: In one or more embodiments, methods for erasing memory devices, and a memory system are disclosed, one such method comprising determining which cells of a sample are not erased, either directly or indirectly. The number of unerased cells in the sample can be compared to a threshold. An erase operation can be performed on the memory block responsive to the comparison until the number of unerased cells is less than the threshold.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: May 17, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Vishal Sarin
  • Non-volatile memory control
    Patent number: 7944762
    Abstract: Methods and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time are useful in the control of concurrent access of memory arrays. One method includes implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays and limiting the number of active arrays operating at one time. The controller is configured to wait for the at least one of the arrays to complete before initiating a transfer to and from a further array.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: May 17, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Sergey Anatolievich Gorobets
  • Multiple-depth STI trenches in integrated circuit fabrication
    Patent number: 7939394
    Abstract: Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: May 10, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Shubneesh Batra, Howard C. Kirsch, Gurtej S. Sandhu, Xianfeng Zhou, Chih-Chen Cho
  • Coarse and fine programming in a solid state memory
    Patent number: 7936599
    Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: May 3, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
  • Canopy modification using computer modelling
    Patent number: RE42439
    Abstract: A method and system for determining canopy coverage to a golf green to assist in increasing sunlight exposure of the green. The system allows users to enter data regarding the golf green, surrounding foliage, and other topographical and man-made features surrounding the green. The system can then plot the sun's path for a specific date and simulate shadows cast on the green by the surrounding foliage and features. Furthermore, the system allows the user to generate what-if data, allowing projected effects on canopy coverage to be viewed before any modifications to the canopy are carried out.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: June 7, 2011
    Assignee: ArborCom Technologies, Inc.
    Inventor: Dan Fulton