Patents Represented by Attorney Leffert Jay & Polglaze, P.A.

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  • Configurable digital and analog input/output interface in a memory device
    Patent number: 8004887
    Abstract: Methods and memory devices are disclosed, for example a memory device that has both an analog path and a digital path that both share the same input/output pad. One of the two paths on each pad is selected in response to command signals that indicate the nature of the signal being either transmitted to the device or read from the device. Each digital path includes a latch for latching digital input data. Each analog path includes a sample/hold circuit for storing either analog data being read from or analog data being written to the memory device.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: August 23, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung-Sheng Hoei
  • Bottom electrode geometry for phase change memory
    Patent number: 8003972
    Abstract: A PCRAM cell has a gradated or layered resistivity bottom electrode with higher resistivity closer to a phase change material, to provide partial heating near the interface between the cell and the bottom electrode, preventing separation of the amorphous GST region from the bottom electrode, and reducing the programming current requirements. The bottom electrode can also be tapered to have a smaller cross-sectional area at the top of the bottom electrode than at the bottom of the bottom electrode.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: August 23, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Composition and method for killing nematodes and weeds in soils
    Patent number: 8003570
    Abstract: A composition for and a method to kill nematodes, weeds, weed seeds and weed rhizomes in soils.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: August 23, 2011
    Assignee: Agro-K Corporation
    Inventor: A. Harry J. Rajamannan
  • Single latch data circuit in a multiple level cell non-volatile memory device
    Patent number: 8004892
    Abstract: A single latch circuit is coupled to each bit line in a multiple level cell memory device to handle reading multiple data bits. The circuit is comprised of a latch having an inverted node and a non-inverted node. A first control transistor selectively couples the non-inverted node to a latch output. A second control transistor selectively couples the inverted node to the latch output. A reset transistor is coupled between the inverted node and circuit ground to selectively ground the circuit when the transistor is turned on.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: August 23, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Tommaso Vali, Giovanni Santin, Michele Incarnati
  • Programming error correction code into a solid state memory device with varying bits per cell
    Patent number: 8006166
    Abstract: Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: August 23, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
  • Charge pump operation in a non-volatile memory device
    Patent number: 8000152
    Abstract: A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load voltages are charged from the charge pump. The first load is removed from the charge pump during a verify operation. The first load voltage is subsequently recharged by charge sharing from the second load voltage so that the charge pump is not initially necessary for recharging the first load voltage.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: August 16, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Chang Wan Ha
  • Analog-to-digital and digital-to-analog conversion window adjustment based on reference cells in a memory device
    Patent number: 7995412
    Abstract: An analog-to-digital conversion window is defined by reference voltages stored in reference memory cells of a memory device. A first reference voltage is read to define an upper limit of the conversion window and a second reference voltage is read to define a lower limit of the conversion window. An analog voltage representing a digital bit pattern is read from a memory cell and converted to the digital bit pattern by an analog-to-digital conversion process using the conversion window as the limits for the sampling process. This scheme helps in real time tracking of the ADC window with changes in the program window of the memory array.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: August 9, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Jung-Sheng Hoei, Frankie F. Roohparvar
  • Method for erasing a semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell
    Patent number: 7995402
    Abstract: A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains the magnetic orientation of the lower magnetic layer of the junction. A current through a selected word line, coupled to the control gate, generates a first magnetic field. A current through a cell select line generates a second magnetic field that is orthogonal to the first magnetic field. This changes the magnetic orientation of the upper magnetic layer of the junction to lower its resistance, thus allowing a write/erase voltage on a program/erase line to program/erase the floating gate.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: August 9, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Parag Banerjee, Terry Gafron, Fernando Gonzalez
  • Charge loss compensation during programming of a memory device
    Patent number: 7995395
    Abstract: A selected memory cell on a selected word line is programmed through a plurality of programming pulses that are incremented by a step voltage. After a successful program verify operation, programming of the selected memory cell is inhibited while other memory cells of the selected word line are being programmed. Another program verify operation is performed on the selected memory cell. If the program verify operation fails, a bit line coupled to the selected cell is biased at the step voltage and a final programming pulse is issued to the selected word line. The selected memory cell is then locked from further programming without evaluating the final program verify operation.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: August 9, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Michele Incarnati, Giovanni Santin, Danilo Orlandi
  • Stacked non-volatile memory with silicon carbide-based amorphous silicon finFETs
    Patent number: 7994566
    Abstract: A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: August 9, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Reducing effects of program disturb in a memory device
    Patent number: 7995400
    Abstract: The programming disturb effects in a semiconductor non-volatile memory device are reduced by biasing unselected word lines of a memory block with a negative voltage followed by a positive Vpass voltage. The selected word lines are biased with a programming voltage. In one embodiment, the programming voltage is preceded by a negative voltage.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: August 9, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Vishal Sarin
  • Methods of operating memory devices including different sets of logical erase blocks
    Patent number: 7990775
    Abstract: Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second set of logical erase blocks. The logical erase blocks of the first set of logical erase blocks each have a first size the logical erase blocks of the second set of logical erase blocks each have a second size different than the first size.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: August 2, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Programming of a solid state memory utilizing analog communication of bit patterns
    Patent number: 7986553
    Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes preprogramming erased memory cells that are to be programmed to a known Vt that is less than the smallest Vt of the possible programmable states. Thus, the subsequent programming pulses start programming all cells from the known threshold voltage.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: July 26, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Method for programming and erasing an NROM cell
    Patent number: 7986555
    Abstract: A nitride read only memory (NROM) cell can be programmed by applying a ramp voltage to the gate input, a constant voltage to one of the two source/drain regions, and a ground potential to the remaining source/drain region. In order to erase the NROM cell, a constant voltage is coupled to the gate input. A constant positive current is input to one of the source/drain regions. The remaining source/drain region is either allowed to float, is coupled to a ground potential, or is coupled to the first source/drain region.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: July 26, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Andrei Mihnea
  • DRAM tunneling access transistor
    Patent number: 7983070
    Abstract: In one embodiment, a first transistor is comprised of a first p+ source region doped in an n-well in the substrate and a first n+ drain region doped on one side at the top of the pillar. A second transistor is comprised of a second p+ source region doped into the second side of the top of the pillar and serially coupled to the top drain region for the first transistor. A second n+ drain region is doped into the substrate adjacent the pillar. Ultra-thin body layer run along each pillar sidewall between their respective active regions. A gate structure is formed along the pillar sidewalls and over the body layers. The transistors operate by electron tunneling from the source valence band to the gate bias-induced n-type channels, along the ultra-thin silicon bodies, thus resulting in a drain current.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: July 19, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Memory array with inverted data-line pairs
    Patent number: 7983085
    Abstract: At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second column of memory cells and the second data line is coupled to the first column of memory cells.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: July 19, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Satoru Tamada
  • Programming in a memory device
    Patent number: 7983088
    Abstract: Methods for programming a memory device, memory devices, and a memory systems are provided. According to at least one such method, a selected memory cell is programmed by a series of programming pulses. The series of programming pulses are configured in sets of programming pulses where each set has the same quantity of pulses and each programming pulse in the set has substantially the same amplitude (i.e., programming voltage). The amplitude of the programming pulses of subsequent sets is increased by a step voltage from the previous amplitude.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: July 19, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Violante Moschiano, Marco-Domenico Tiburzi, Giovanni Santin, Giulio G. Marotta
  • On-chip temperature sensor
    Patent number: 7978556
    Abstract: A temperature invariant reference voltage and a temperature variant physical quantity, such as a voltage or current, are generated. The temperature variant physical quantity changes in response to a temperature of the integrated circuit. A temperature sensor circuit generates a voltage that is linearly dependent on the temperature. A level generator circuit generates 2n?1 voltage levels from the reference voltage. A comparator circuit, such as an analog-to-digital circuit, compares the voltage from the temperature sensor to the 2n?1 voltage levels to determine which level is closest. An n-bit digital output of the resulting level is proportional to the temperature of the integrated circuit.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: July 12, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Macerola, Giulio-Giuseppe Marotta, Marco-Domenico Tiburzi
  • Data line management in a memory device
    Patent number: 7978511
    Abstract: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods are provided. According to at least one such method, multiple pages of memory cells are inhibited during a programming operation such that memory cells enabled for programming are separated by two or more inhibited memory cells of the same row of memory cells regardless of the intended pattern of data states to be programmed into that row of memory cells.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: July 12, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Andrew Bicksler
  • Fully depleted silicon-on-insulator CMOS logic
    Patent number: 7973370
    Abstract: A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: July 5, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes