Abstract: A stepping motor driver is adjusted to minimize resonance by adjusting a variable frequency source to adjust the fundamental frequency of the drive to the frequency of a filter, driving the driver and motor with the adjusted frequency source, sensing the motion of the motor and providing the sensed motion to an indicator through the filter. The driver is adjusted to minimize the indication. Adjustment at various harmonics are performed by using 1/N the adjusted frequency, where N is the harmonic of interest.The improved driver includes a plurality of voltage sources adjustable for resonance compensation at the fundamental frequency and 1/N thereof. DC offset, relative gain and orthogonality of the motor driver signal adjustments are provided.

Abstract: A buffer having a first and second complementary IGFET input inverter connected in series and an output including a bipolar emitter follower with its base connected to the output of the first inverter, a second bipolar transistor connected in series with the emitter follower with its base connected to the output of the second inverter and an IGFET connected between the junction of the bipolar transistors and a voltage supply terminal and with its gate connected to the input of the first inverter. The output IGFET pulls the buffer output up to the supply voltage when the emitter of the emitter follower is at the supply voltage minus V.sub.BE.

Abstract: Specific impurity concentration regions are used for the simultaneous formation of CMOS devices and complementary bipolar transistors to produce high voltage, high performance bipolar transistors. The last diffusion step for shallow P.sup.+ and N.sup.+ emitter regions and contact regions is performed without a separate diffusion cycle. The formation of the gate oxide at a relatively low temperature is followed immediately by the formation of an undoped polysilicon gate layer. The polysilicon gate layer is doped to a reasonable resistance and also forms a first level interconnect. Phosphorous doped CVD silicon oxide is formed thereover and the top surface is treated with additional phosphorous to produce tapered contact apertures therethrough when etched. A layer of metal is applied and delineated to form contacts to the substrate regions and to form the second level of interconnects.

Abstract: A vertical insulated gate field effect transistor having a first conductivity layer, a second conductivity layer thereon, a third first conductivity layer thereon, a groove extending from the surface of the third layer through the second layer into the first layer, a layer of insulation and gate material in the groove and a shallow first conductivity vertical region extending from the third layer into the second layer along the groove to form a short channel in the second layer with a shallow device junction.The device is fabricated by masking the three semiconductor layers and etching the third layer and part of the second layer to form a groove, diffusing second conductivity impurities to a shallow depth in the groove, continuing the etching to extend the groove through the second layer into the first layer. A layer of insulation and gate material are formed in the groove to produce the vertical channel.

Abstract: A memory cell having two mesa bipolar transistors separated by a valley in which two doped polycrystalline load resistors are formed. Doped polycrystalline conductors connect the resistors to a respective backside metallic collector contact which is between a support structure and a transistor and to a respective base.The cell is fabricated by removing a substrate upon which was formed an epitaxial layer and top support, applying a backside metallic layer, forming a bottom support, removing the top support, etching the epitaxial layer to form mesas, etching the backside metal to form discrete contacts, and forming multi-level resistors and conductors in the valley between the mesa transistors separated by insulative material.

Abstract: Low resistance contact paths to selected buried layers in dielectrically isolated islands are formed by V-etching the selected island moats in a substrate, non-selectively diffusing impurities into the surface of the substrate and selected moats, V-etching to form all the moat structure, forming a dielectric layer on said surface and moats, applying support material to over-fill said moats and cover said surface, removing the opposite surface of said substrate to expose support material, and forming devices in said opposite surface.

Abstract: Integrated circuits in dice on a wafer are qualified by providing two sets of conductors connected to each die by fusible elements, biasing the dice using said conductors during exposure to a qualifying environment, testing the fusible elements, removing the conductors and testing the circuits. Where the environment is gamma radiation, the fusible elements are tested before annealing of radiation damage and the circuits are tested before and after annealing.

Abstract: An adjustable container primarily for use as a tool or utility box for pickup trucks. The adjustable container is formed of two telescopically engaging sections, each of which includes a pivoted top closure member, integrally molded side and bottom supports and an inner shelf support. With the exception of the interfitting parts of each section, the two sections are preferably identical. The bottom supports are hollow and serve as a reservoir to hold liquids that may spill within the container.

Abstract: A refractory floor for the firebox of a heating unit including front, side and rear vertical portions with top surfaces inclined towards the respective wall. The rear and side vertical portions exceed the height of a grate or andirons positioned on the refractory floor.

Abstract: A lateral PNP transistor is formed by diffusing N type inpurities into an N type layer to form base contact region and base region, diffusing P type impurities into the N base region and N layer to form emitter and collector regions respectively, and counter doping the layer area between the N base region and the collector region. The counter doping is performed through a non-critical mask aperture extending between the emitter and collector regions.

Abstract: A narrow woven stretch fabric is formed from bare elastomeric warp threads separated by high shrink warp threads and from a high shrink weft thread. The edge elastomeric warp threads are loosely wrapped with heat set yarn. These edge threads, which are under the same tension as the other elastomeric warp threads, are wrapped between the supply and the loom. The weft thread is interwoven at a low weft per inch and the fabric is heat treated to shrink the non-elastic high shrink threads and corrugate the elastomeric threads without heat setting. The wrapping device and the surface feed rollers for the elastomeric threads are driven by the loom drive at appropriate speeds.

Abstract: A new encoder for an analog to digital converter of the successive approximation type incorporates instrumentation amplifier and signal sample and hold functions within the encoder proper, thereby substantially simplifying the converter circuitry. An input analog current signal is applied to a sample and hold capacitor within the encoder through the encoder comparator at a time when the weighted reference signal to the comparator is set to zero. The capacitor stored analog voltage is subsequently applied to the encoder summing node and the encoding sequence ensues. The encoder may be provided with offset and gain correction circuitry, conventionally found exterior to the encoder. In one embodiment of the invention, offset correction is effected using the signal sample and hold capacitor.

Abstract: Integrated circuits in dice on a wafer are biased burn-in qualified by providing two sets of conductors connected to each die by fusible elements, biasing the dice using said conductors during the high temperature burn-in, testing the fusible elements, removing the conductors, and testing the circuits.

Abstract: A rolled material guide and cutter attachable to a pre-existing rolled material holder is provided. The rolled material guide and cutter comprises a pair of attachment members that attach to the brackets of the pre-existing roll holder, an interconnecting member between the pair of attachment members and a cover member pivotally connected to the attachment members. The cover member and interconnecting member form a channel through which the paper is guided. A tearing edge is provided to tear the material at the exit of the channel.

Abstract: The moisture content of a hermetically sealed semiconductor device is a function of the dew point of the cavity atmosphere which is the temperature of maximum surface conductivity. A pattern of interdigitated thin film aluminum conductors is provided on an impurity free, non-porous silicon oxide insulative substrate. The surface conductivity of this structure rises as moisture condenses onto and between the conductors as the temperature is reduced at a slow controlled rate to the dew point temperature. The amplitude of the maximum surface conductivity is proportional to ionic impurity concentration.

Abstract: Fuses and interconnects are fabricated by applying a metallic layer on a substrate and a fusible layer on the metallic layer. Portions of the fusible layer are removed to define discrete fuse elements having a necked portion. Portions of the metallic layer are removed to define interconnects. A portion of the metallic layer coextensive with the necked portion of the fuse elements is removed by selective side etching to form tapering portions separated by a gap without etching of the interconnects. The interconnects are protected from side etching by a separate mask layer or a mask layer used to form the interconnects may be heated to flow down over the sides of the interconnects.

Abstract: The first fire voltage of amorphous memory devices are reduced by forming the storage element of two layers, the first being in the crystalline state and the second being the amorphous state. The process deposits a first layer of switchable material and raises the temperature to crystallize the first layer. The wafer is then cooled and the remainder of the switchable material to form the storage element is deposited in an amorphous state.

Abstract: A memory array wherein each memory cell includes a resistive device which switches from a high to a low resistance state when a potential above its programmable threshold is applied and including a reference cell per word line having a reference switchable resistive device. Using a ramp addressing potential, the array output is disabled by an output disable circuit after a reference resistive device switches which is after the switching of an addressed low threshold resistive device cell and before the switching of an addressed high threshold resistive device cell.