Abstract: A single circuit breaker housing containing a circuit breaker to disconnect the line terminal from the load terminal for a current overload and means to disconnect and reconnect the line terminal from the load terminal for power management. The power management means, activated by an internal or external timer or remote modulated signal, may include a switch in series with circuit breaker contacts or fusible element or electromechanical device to set and reset the circuit breaker contacts. The external timer or other remote activation signals are provided via external terminals on the housing or via a wireless or powerline modulated signal. Electro-optical isolator functionally interconnects and electrically isolates the power management means and the circuit breaker.

Abstract: A bipolar transistor process and device wherein the transistor is fabricated within a laterally isolated device region, into which is formed a lateral intradevice isolation groove prior to formation of device/active and contact regions. The lateral intradevice isolation groove with the lateral device isolation assists in self-alignment of device regions. The lateral intradevice isolation permits the simultaneous formation through a single mask of an active region and a contact region for a different active region both on the same planar surface of a semiconductor substrate and facilitates extremely close spacing of active regions at the planar surface.

Abstract: A reusable temporary cover for indoor house plants to retain moisture for the plant. The cover is formed of flexible transparent plastic sheet material with tie means to completely enclose a house plant and includes a water retention portion to catch and store excess water. By enclosing the plants after watering, a terrarium effect is produced and moisture is retained within the cover for a long period of time.

Abstract: A support stand including a base and a thin platform extending cantilevered from the base. The height and angle of the platform is adjustable. The platform is flexible spring steel to accommodate the appendage to be cast and is readily removed by sliding it out of the completed cast.

Abstract: A metallic ground grid is fabricated by forming a conductor on the isolation barrier of an integrated circuit through openings in a first insulated layer to a depth less than the first insulated layer, forming a second insulated layer on said first conductor to the height of the first insulated layer, and interconnecting selected areas of the integrated circuit and the first conductor through openings in the insulated layers by a second conductor.

Abstract: A method and apparatus for measuring bio-electrical potential in female mammalia to determine ovulation.The apparatus includes a first and second container operable to contain an ionic medium and to receive in one container at least one finger of one hand of a test subject and a first active probe and to receive in the other container at least one finger of the other hand of the test subject and a second active probe. An electrical network for measuring electronic potentials in the millivolt range is connected to the active probes and functions to measure increases in potential emitted by the test subject upon ovulation.

Abstract: A Schottky barrier diode is formed in a low impurity concentration N-type substrate by ion implanting N-type impurities to form a deep region having increased impurity surface concentration of at least 10.sup.16 carriers per cubic centimeters, forming P-type guard ring in the deep N-type region and forming an N.sup.+ contact region in the deep N-type region. NPN transistors can be fabricated in the original low impurity substrate or in an ion implanted substrate region having a lower breakdown voltage. Schottky clamped NPN transistors formed in the low impurity substrate include ion implanted regions interior to a base ring and extending down into a buried N.sup.+ collector region as does an ion implanted surface collector contact region having an N.sup.+ contact area.

Abstract: A RAM cell having a pair of transistors formed in two adjacent wells laterally separated from each other and surrounded laterally by a common doped polycrystalline semiconductor moat. Dielectrical insulation separate the wells from the moat. The moat is discontinuous, forming thereby a pair of resistors connected together at one end and disconnected at the discontinuity. Surface contacts bridge adjacent areas of the well and the moat which are of the same conductivity type whereby the moat forms the load resistor for the transistor. Each transistor includes a second emitter.First level interconnects include a first interconnect interconnecting an emitter from each transistor, a second interconnect parallel to the first contacting the connected end of the moat resistors, a pair of interconnects each interconnecting the bridge contact of one transistor to the base of the other, and a pair of contacts for the other emitter regions.

Abstract: V-shaped lateral dielectric isolation grooves divide a semiconductor layer into a plurality of regions. The oxide layer above the polycrystalline material in the grooves is thicker than the field oxide layer on the semiconductor layer to prevent the creation of retrograde surface profiles and mask the polycrystalline material during self-aligned device fabrication in the semiconductor layer. The field oxide is formed on the semiconductor layer before the isolation groove fabrication and prevented from increasing in thickness by an oxide inhibiting layer during the isolation groove fabrication.

Abstract: A method of providing permanent identification markings to gemstones such as diamond crystals by irradiating the gemstone with protons in the desired pattern. The proton bombardment results in a reaction converting the bombarded area into a different crystal lattice than that of the pre-irradiated stone.

Abstract: Fuses and interconnects are fabricated by applying a metallic layer on a substrate and a fusible layer on the metallic layer. Portions of the fusible layer are removed to define discrete fuse elements having a necked portion. Portions of the metallic layer are removed to define interconnects. A portion of the metallic layer coextensive with the necked portion of the fuse elements is removed by selective side etching to form tapering portions separated by a gap without etching of the interconnects. The interconnects are protected from side etching by a separate mask layer or a mask layer used to form the interconnects may be heated to flow down over the sides of the interconnects.

Abstract: An amorphous memory cell operated to have a first logic state represented by a high resistance state, substantially no crystal structure and a first threshold level and a second logic state represented by a high resistance state, microcrystal structure and a threshold level lower than the first threshold level. The logic state is read by monitoring the electrical characteristic of the cell for a constant voltage read pulse at a time greater than the threshold switching delay duration for the first logic state and less than the threshold switching delay duration for the second logic state at the read pulse voltage.

Abstract: A CMOS voltage multiplier circuit comprised of one or more multiplier cells each of said cells including two P-channel devices functioning as switching elements to connect a cell contained capacitance in parallel across a voltage supply during one half of a cycle and a single N-channel device for connecting the capacitance in series with the supply during the other half of the cycle. An output stage is provided which includes a transfer device and a modified multiplier cell for driving the transfer device.

Abstract: An amplifier for use as on the output buffer for semiconductor memories including an amorphous element added to a push-pull configuration to allow conversion between push-pull and open collector nonvolatile configurations by electrically altering the impedence of the amorphous element.

Abstract: A waterbed mattress construction includes baffle means for dampening water wave action. The dampening means comprises one or more flexible plastic strips welded to the interior bottom surface of the mattress and flotation means welded to the other end of the strips. The flexible strips may be in the form of an open box with approximately the same configuration as the waterbed mattress. The flotation means is a single piece of foam or other material which causes the plastic strips to float to the top of the water in the mattress.

Abstract: A free-standing unit for heating air in a U-shaped channel surrounding a fire box having a pair of spaced vertical vents for directing the heated forced air to converge in front of the fire box opening to limit air flow towards said openings. Mesh in the vertical vents directs the forced air downward to be combined with the hot forced air from a bottom horizontal vent. A baffle plate depending from the top of the fire-box adjacent the flue port and an opening along the top of the doors ignite the gases adjacent the top and directs some gases back into the fire. By forcing heated air at a low level and drawing cool air from a high level, the air being heated is of a uniform temperature. A hood extending along the top edge of the fire box opening diverts exiting gases back into the fire box. A thermostatically controlled blower creates the forced air and cools the fire box walls.

Abstract: A method of forming fuses and two level interconnects including applying a layer of fusible material on an insulating layer and through contact apertures, cleaning said fusible layer by sputter etching, applying a layer of metallic material by sputtering, selectively patterning the metallic layer to form a top layer of contacts and interconnects and selectively patterning the fusible layer to form fusible elements and to form a bottom layer of contacts and interconnects.

Abstract: A crack free layer of GaP is epitaxially deposited on a silicon phosphide surface of a silicon substrate having an (III) orientation. The silicon substrate is prebaked on a carbide coated susceptor with palladium diffused hydrogen at about 1200.degree. C. and pretreated with phosphine at about 1140.degree. C. to form the silicon phosphide surface. The temperature is lowered to 800.degree.-900.degree. C. in the presence of phosphine and trimethyl gallium is introduced at a ratio of 1 to 10 with the phosphine. Cracks in the gallium phosphide are prevented by roughing the bottom non-phosphide surface of the silicon substrate such that the roughed surface is under compressive stress and induces tensile stress on the phosphided surface to reduce the compressive stress produce by gallium phosphide layer when the substrate is annealed at about 1200.degree. C.

Abstract: A method and apparatus of preplating ties including traversely aligning ties on a path, conveying along the path ties relative to a pair of plate guides, positioning a pair of plates on each tie adjacent the guides, attaching the plates to the tie by partially driving fasteners, continue aligning the plates relative to each other by conveying the tie relative to the guides and securing the plates to the tie during alignment by completing the driving of the fasteners. A tie guide is provided having a fixed guide parallel to the path and a biased pivotal guide extending at an angle to the fixed tie guide.

Abstract: A metallic ground grid is fabricated by forming a conductor on the isolation barrier of an integrated circuit through openings in a first insulated layer to a depth less than the first insulated layer, forming a second insulated layer on said first conductor to the height of the first insulated layer, and interconnecting selected areas of the integrated circuit and the first conductor through openings in the insulated layers by a second conductor.