Abstract: Data is digitally sampled at intervals, and these samples are stored for a fixed period. During this period the samples are also processed to select certain characteristics, such as maximum, minimum, average, etc., and these abstract indicators are stored and updated. Then, at some longer interval, the abstract is stored in another data block, and this data block of abstracts is also continuously monitored to select the maximum, minimum, etc., to produce a higher abstracted sample. The process of storage of samples and continuous selection can be repeated for even higher abstraction. Thus, the important characteristics are preserved, but the quantity of data to be stored is greatly reduced.

Abstract: A memory device is presented having the option, using simple means, of using one basic chip for different pin-outs or chip configurations. The metal and pin-out option implementation are formed by: 1) a dual-function pad and associated circuitry with an option for either an Input/Output or an Input-only configuration and 2) rotation of the chip with respect to the orientation of the DIP (dual in-line package). The implementation of this invention has decreased area requirements and better performance capabilities than those of known prior-art implementations.

Abstract: An alignment system (30) is provided for use during the lithography process of producing multiple layer (24-26) integrated circuits. The location of each previous layer (24-26) in the integrated circuit is measured and evaluated with respect to each other and the wafer (14). The next layer is placed on the wafer (14) in a manner which optimizes its alignment relationship to each of the previous layers (24-26). Weighting factors are used to optimize alignment in multiple layer (24-26) integrated circuits.

Abstract: The present invention provides a system and method for performing speaker verification on a spoken utterance. The present invention includes a verification template generator (40) which generates speaker-dependent verification templates for each possible spoken item that may be in the spoken utterance. A speech recognizer (42) performs speech recognition functions on the spoken utterance. A frame mapper (44) marks the beginning and ending of each spoken item within the spoken utterance. Verification module (46) generates a verification signal in response to verifying a minimum number of the spoken items within the spoken utterance being matched with the speaker dependent verification templates.

Abstract: A semiconductor memory device (10) includes a plurality of row address inputs (RA0-RA8), and a plurality of column address input (CA0-CA8) lines. A plurality of main memory subarrays (122) include a plurality of memory cells (122). A plurality of redundant memory arrays are associated with the main memory arrays. Column redundancy circuitry (68) receives column addresses (CA3-CA7) for determining if a match occurs between the received column addresses and the stored redundant column information.

Abstract: A DMD display system includes an inverse gamma look-up-table (50) for converting raster scanned, gamma corrected video data of 8 bits to 12 bits inverse gamma data with 8 most significant bits (msb) and 4 least significant bits (lsb). The 8 msb are coupled to the micromirror of the DMD display (10) and the four lsb are delayed and halved such that one half of the lsb is added to the next pixel in the horizontal scan and one-half of the lsb is added to the next vertical pixel one line length delayed.

Abstract: A semiconductor memory device 40 includes an array of storage cells 130, addressable by row and column and specifically designed for testing. Row and column addresses are decoded to access a row and plural columns simultaneously. A test data bit to be written into the storage cells is replicated and stored into as many storage cells at once as there are columns simultaneously accessed. Upon readout for a comparison test, plural occurrences of the stored test data bit are compared with each other and with an expected data bit within parallel comparator circuitry 140 located within the memory device. A pass/fail signal (on lead 170) from the parallel comparator circuitry is transmitted to the memory device tester 30 for final defect analysis and correction. When a failure/defect is detected, information representing the address and the type of failure are stored in the memory device tester. A memory device test method also is described.

Abstract: A scan cell (51) for use at an input/output terminal includes memory circuitry (Mem 1) for storing test data from a test data path, and a latching circuit (S4, LOB; S6, LIB) connected to the memory circuitry for receiving and selectively latching the test data stored in the memory circuitry. The input/output terminal has an input buffer (IB) and an output buffer (3SOB) associated therewith, and the latching circuit includes one of the input buffer and the output buffer.

Abstract: An emulator for emulating operations of data processing circuitry normally connected to and cooperable with a peripheral circuit includes serial scanning circuitry connectable to the peripheral circuit in substitution for the data processing circuitry. The serial scanning circuitry provides to and receives from the peripheral circuit signals which would normally be provided and received by the data processing circuitry. The serial scanning circuitry is connectable to an emulation controller for permitting serial data transfer between the emulation controller and the emulator. The emulator further includes control circuitry connected to the serial scanning circuitry and connectable to the emulation controller. The control circuitry permits the serial scanning circuitry to provide and receive the aforementioned signals while serial data is being transferred in a continuous serial data stream between the emulation controller and the serial scanning circuitry.

Abstract: The on-chip endurance test (Autocycle) and the parametric characterization test (Auto VccMax/Min) of this invention save test time and hardware by performance automatically on the memory chip upon transmittal of a single command (CONTROL CODE) to the chip from the tester. The automated test procedures of this invention run faster because the on-chip tester requires fewer externally issued commands (CONTROL CODEs) and requires fewer external status checks. The procedures of this invention permit the external tester to have a smaller number of input/output pins (CONTROL), decreasing the cost of the external test hardware. Specifically, the endurance test (Autocycle), automatically cycles the memory chip through any combination of programming, erasing, and/or compaction operations until either a failure has been detected or the required number of the test cycles has been completed.

Abstract: An improved image scaling filter for a video display where a coefficient value for the closest input lines to a given output line that are less than two line lengths from the given output line are determined by cubic interpolation using the line distances. The input lines are multiplied by the coefficient for that line and the multiplied closest input line values are summed to determine the output line value.

Abstract: The method of this invention prevents transient currents at high-frequency disable cycles and disables DC current paths after a minimum delay time, thereby reducing power dissipation. This invention includes a delay circuit functioning to prevent disablement of DC paths where chip-disable times occur at intervals below a minimum duration. The result is a decrease in the number of undesired voltage drops on internal power buses due to transient currents. The method detects external chip-disable pulses that occur before a minimum time duration, then prevents those pulses from powering down internal direct-current paths. At the same time, the output driver high impedance functionality of the chip-disable signal is preserved.

Abstract: The method comprises the steps of converting the algorithm into a control flow graph having a plurality of nodes, each node representing at least one of the plurality of statements. The control flow graph further includes a conditional branching node for the data-dependent conditional branching statement. Reverse dominators are then computed for each of the plurality of nodes, from which a meet point node for each conditional branching node is derived. The method further provides for constructing a shadow symbol table housing the variables, and constructing a duplicate shadow symbol table for each possible value of the datum in response to the conditional branching node. The conditional branching node is also evaluated by assuming each possible value of the datum for each branch and assigning symbolic values to each of the variables in the shadow symbol table. The nodes contained in each branch are evaluated until the meet point node is reached. The duplicate shadow symbol tables are then merged.

Abstract: A data processing device includes a data processing core (43), a cache (33) connected to the core and having a cache width, and a bus (31) for receiving from an information source external to the data processing device a burst of information having a width which exceeds the cache width by a width difference. The cache is coupled to the bus to receive and store a first portion of the burst which is equal in width to the cache width. A storage circuit (35) is coupled to the bus to receive and store a second portion of the burst corresponding to the width difference, and the storage circuit has an output coupled to the core.

Abstract: A nonvolatile memory array has a plurality of diffused horizontal source lines (17), each source line (17) positioned between a pair of parallel horizontal stack conductors (ST). The plurality of the diffused horizontal source lines (17) are connected to at least one common vertical source conductor (17a). The common vertical source conductor (17a) includes continuous diffused regions (11) under each of said pair of parallel horizontal stack conductors (ST). In addition, the common vertical source conductor (17a) includes a metal conductor coupled to the continuous diffused regions at contacts (SC) located between the pairs of parallel horizontal stack conductors (ST). As a result, the stack conductors (ST) are straight. The straight-stack conductor (ST) configuration allows use of less space between a vertical source conductor (17a) and adjacent drain-column lines (18) and eliminates any need for use of vertical columns of dummy cells (10).

Abstract: A serial scan design permits shift element (71) to selectively access more than one node (43) of a target circuit (14).

Abstract: In a multi-sector nonvolatile memory array in which each memory cell has a drain coupled to a bitline, each memory cell of each sector has a source coupled to a common array-source line, each memory cell in a row of the first sector has a control gate coupled to a wordline and each memory cell of a row in another sector has a control gate coupled to that wordline, a method for programming a memory cell in one sector of said method includes connecting at least the second common array-source line to each bitline coupled to drains of columns of memory cells in the another sector, then biasing at a positive voltage both the common array-source line and the bitlines coupled to drains of memory cells in columns of the another sector, and then applying a programming voltage to the selected wordline coupled to the control gate of the selected cell in the first sector.

Abstract: An integrated circuit includes a terminal which is accessible externally of the integrated circuit, and circuitry (LOB) coupled to said terminal and operable to latch at said terminal a signal applied to said terminal by a source (ICT) external to said integrated circuit.

Abstract: A method for forming poly-silicide conductors (CG,GAP) on a semiconductor device (10) includes forming a layer (14) of doped polysilicon over a region of the device (10), then depositing a layer (15) of refractory metal on the layer (14) of doped polysilicon. The layer (14) of doped polysilicon and the layer (15) of refractory metal are then annealed to form a poly-silicide layer (PSL). The poly-silicide layer (PSL) is then etched to form the poly-silicide conductors (CG,GAP).

Abstract: A circuit (51) for converting a pair of precharged dynamic logic signals into a static logic signal includes a first input (61) to receive one of said dynamic logic signals, a second input (67) to receive the other of said dynamic logic signals, and an output (Qout). A first signal path from said first input to said output includes only two logic gates (63,69), and a second signal path from said second input to said output includes only one logic gate (69).