Abstract: A data processing system includes a plurality of synchronous random access memory devices, a data processor, and a time skewing circuit interposed between the data processor and the plurality of synchronous memory devices. The time skewing circuit imparts different increments of delay time into memory clock and address signals transmitted to different ones of the synchronous memory devices, imparts different increments of delay time into various control signals, and imparts a uniform increment of delay time into several write enable signals. The read enable signals and the write enable signals are used for loading data into data storage devices, which are a part of the time skewing circuit that is interposed between the data processor and the synchronous memory devices.

Abstract: An electrical circuit includes a serial scan test architecture having first and second separate serial scan paths respectively coupled to first and second portions of the electrical circuit for permitting data to be scanned through the electrical circuit for testing thereof. The first serial scan path is operatively enabled while the second serial scan path is also operatively enabled, thereby permitting concurrent scan testing of the first and second portions of the electrical circuit. Test signals are transferred between the first serial scan path and the first portion of the electrical circuit and between the second serial scan path and the second portion of the electrical circuit while serial test data is being transferred in first and second continuous serial data streams through the first and second serial scan paths, respectively.

Abstract: To ensure proper electrical insulation under thick-field isolation regions (23) grown in triple-well structures, the channel-stop impurity (30) is implanted using multiple doses at different energies, depending on the oxide thickness of the thick-field isolation regions (23). The split-implant procedure results in much wider process variation windows for the thick-field isolation regions (23). Process variations include oxide thickness of grown oxide, implant energy/dose and reduced thickness caused by wet de-glazing steps.

Abstract: The invention discloses a semiconductor package having two rows of interdigitated leads. The two rows of leads (14, 16) are affixed on and extend from one side of the semiconductor package (10). The two rows of leads (14, 16) are interdigitated with each other in a non-contacting manner. The end portions of the leads (17) are further shaped to form a contact surface for soldering to electrical conductors on a printed circuit board.

Abstract: The method of this invention allows use of a smaller wordline voltage Vp1 during programming. In addition, the method results in a relatively narrow distribution of threshold voltages Vt when used to flash program an array of memory cells (10). The method of this invention increases compaction gate-current efficiency by reverse biasing the source (11)/substrate (23) junction of the cell being programmed. The reverse biasing is accomplished, for example, by applying a bias voltage to the source (11) or by placing a diode (27), a resistor (29) or other impedance in series with the source (11). The reverse biasing limits the source current (Is) of cell being programmed and of the entire array during flash-programming compaction.

Abstract: A data processing system (10) includes a register bit structure (27) which can be hard-wired (37, 39) but is also selectively configureable for read/write operation.

Abstract: A dual-port memory having an on-chip color register for storage of input data for use in multiple write cycles is disclosed. The color register is written to during a special cycle, which is enabled by a special function pin in conjunction with the write enable and transfer enable function pins, each of which have their logic state latched in during the row address strobe signal. A second type of special cycle causes a multiplexer to select the contents of the color register, rather than the latched data state of the data input terminals, for the data to be written to the selected memory cells. The use of the color register may be used in conjunction with a mask register, where the writing of certain input/outputs is inhibited. In addition, a block write feature may be incorporated with the color register so that, in another type of special cycle, multiple columns per input/output can be simultaneously written with the contents of the color register.

Abstract: A synchronous random access memory is arranged to be responsive directly to a system clock signal for operating synchronously with the associated microprocessor. The synchronous random access memory is further arranged to either write-in or read out data in a synchronous burst operation or synchronous wrap operation in addition to synchronous random access operations. The synchronous random access memory device may be fabricated as a dynamic storage device or as a static storage device.

Abstract: The present invention provides a method and system, for use with a computer integrated management system, to classify and serve as the data and information repository for a process or product specification and to classify groups of process resources. The Process Type method provides information to describe the outcome of a process. The organization describing a Process Type includes three basic components. The first component is an action. The action component describes what is to be done by the process. The second component is material. The material component describes the element upon which or with which the action described by the action component is performed. The third component is technology. The technology component describes the resource which performs the action described by the action component with or upon the material described by the material component. The resulting Process Type is then used to control a process or the generation of a product to achieve a desired result.

Abstract: Distributed buffering memory device (10) is provided which includes memory circuitry (12) located therein and independent buffering circuitry (16). Device (10) can be used in an array of devices where buffering circuitry (16) is employed to buffer the signals necessary for the array. Each independent buffer is employed to buffer a signal and supply that signal to a bank unique input bus which is used to drive the inputs of the array.

Abstract: A vertical memory cell EPROM array (FIGS. 1, 1a and 1b) uses a vertical floating gate memory cell structure that can be fabricated with reduced cell area and channel length. The vertical memory cell memory array includes multiple rows of buried layers that are vertically stacked --a drain bitline (34) over a source groundline (32), defining a channel layer (36) in between. In each bitline row, trenches (22) of a selected configuration are formed, extending through the drain bitline and channel layer, and at least partially into the source groundline, thereby defining corresponding source (23), drain (24) and channel regions (25) adjacent each trench. The array can be made contactless (FIG. 1a), half-contact (FIG. 2a) or full contact (FIG. 2b), trading decreased access time for increased cell area.

Abstract: An extended-life method for soft-programming at least one floating gate memory cell (10) includes connecting the substrate and the source (11) to a reference voltage, then applying to the control gate (13) a soft-programming voltage, the soft-programming voltage being between thirty and sixty percent of the voltage used to hard-program the cell. Increasing voltages are applied to the drain (12), while measuring the current flow into the drain (12). A specific drain (12) voltage, less than or equal to that value of drain (12) voltage at which the current flow into the drain (12) reaches a first peak, is chosen. With the substrate at reference voltage, the cell (10) is soft-programmed by applying to the drain (12) a first voltage slightly less than or equal to the specific drain (12) voltage; by applying to the source (11) a non-negative second voltage less than the specific drain (12) voltage; and by applying to the control gate (13) a third voltage no greater than the soft-programming voltage.

Abstract: An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (21). Each memory cell includes a source region (11) and a drain region (12) formed in a shared drain-column line (19), with a corresponding channel region in between. A Fowler-Nordheim tunnel-window (13a) is located opposite the channel over the source-column line (17) connected to source (11). A floating-gate conductor (13) includes a channel section (29) and a tunnel-window section (28). The floating-gate conductor is formed in two stages, the first stage forming the channel section (29) and the tunnel-window section (28) from a first-level polysilicon. This floating-gate channel section (29) is used as a self-alignment implant mask for the source (11) and drain (12) regions, such that the channel-junction edges are aligned with the corresponding edges of the channel section (29).

Abstract: A data processing system includes a plurality of synchronous random access memory devices, a data processor, and a time skewing circuit interposed between the data processor and the plurality of synchronous memory devices. The time skewing circuit imparts different increments of delay time into memory clock and address signals transmitted to different ones of the synchronous memory devices, imparts different increments of delay time into various control signals, and imparts a uniform increment of delay time into several write enable signals. The read enable signals and the write enable signals are used for loading data into data storage devices, which are a part of the time skewing circuit that is interposed between the data processor and the synchronous memory devices.

Abstract: A design to attain a pass transistor for a 256 Mbit DRAM part. The transistor having a gate length of about 0.3 .mu.m, a t.sub.ox of about 85 .ANG., which is much thicker than the .about.65 .ANG. t.sub.ox for 0.25 .mu.m logic technology, a V.sub.WL of 3.75 V, a V.sub.sub of -1 V, arsenic LDD and a boron concentration in the channel region of about 2.7.times.10.sup.17 /cm.sup.3 are the desired technological choices for 256 Mbit DRAM devices.

Abstract: A distributed network monitor system distributes the network monitoring function among each of the nodes of a multiple network system, such that monitor software resident in each node is responsible for providing status information about that node and its communications links. At predetermined monitoring intervals, a circulating status table (CST) (FIG. 4) is circulated to all of the on-line nodes, with each node updating the CST with its link and status information. The monitor software (FIG. 1) includes a servicer task (22), a node monitor task (24), and a packet manager task (26), with intertask data transfers being implemented through a monitor region (28) in memory. In addition to link and node status information, the CST includes information about links that are in an intermittent condition (i.e., links with significantly degraded statistical performance).

Abstract: A method (40) and system (10) are provided for knowledge based design. Conceptual model elements (12) are stored. Also, stereotype knowledge bases (14) are stored. Ones of the conceptual model elements (12) are matched with ones of the stereotype knowledge bases (14) to select a closest matching one (16) of the stereotype knowledge bases (14). Design model elements (18) are generated by applying scripts in response to the selected stereotype knowledge base (16).

Abstract: Each element of a database may have multiple versions; the versions are partitioned into branches, and versions of a branch are ordered linearly according to their timestamps. Branches are timestamped and related to one another by a version graph. Each version of an element of a database is represented by a unique identifier, a timestamp, a branch name and a value. A new version of an element associated with a branch is created in response to an operation associated with the branch which would modify the element. An object graph in the database is represented independent of the branches and version; an application coded for elements in one version (and branch) can be reused for the same elements in a different version and (different branch) without any re-coding effort. Methods for long duration transactions, cooperative transactions and schema evolutions are provided.

Abstract: Sense amplifier circuitry (SC) includes a differential amplifier (A) having a reference input and a memory input. The output of a first sense amplifier (SA1) is coupled to the reference input of the differential amplifier (A) and to the input of a second sense amplifier (SA2). The output of the second sense amplifier (SA2) is coupled to the memory input of the differential amplifier (A) and to the input of the first sense amplifier (SA1). The first sense amplifier (SAR) and the second sense amplifier (SA2) include identical mirror transistor circuits (M1, M2, M3, M4).

Abstract: An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source (11) and a drain (12), with a corresponding channel (Ch) between. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the sources (11) and drains (12), such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). Each memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) to the source (11).