Abstract: The signal to noise ratio of a telephone transmission line used for facsimile is determined in one preferred embodiment by notch filtering the received CED signal at the calling unit. The total CED signal received representing signal plus noise (S+N) is processed with the filtered CED signal representing noise N according to 20.multidot.log ([(S+N)-N]/N.

Abstract: The erasing method of this invention results in a relatively narrow distribution of threshold voltages when used to flash erase a group of floating-gate-type memory cells (10). Each cell includes a control gate (14), a source (11) and a drain (12). The method comprises connecting the control gates (14) to a control-gate voltage (Vg), connecting the sources (11) to a source voltage (Vs) having a higher potential than the control-gate voltage (Vg) and connecting the drains (12) to a drain subcircuit (DS) having, in at least one embodiment, a potential (Vd) between the control-gate voltage (Vg) and the source voltage (Vs), the drain subcircuit (DS) having a sufficiently low impedance to allow current flow between the sources (11) and drains (12) at a time during the erasing operation. The drain subcircuit (DS) allows for optimum threshold voltage distribution and a part of the drain potential (Vd) may be fed back to arrest the erase process at an optimum point.

Abstract: An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source region (11) and a drain region (12), with a corresponding channel region between. A Fowler-Nordheim tunnel-window (13a) is located over the source line (17) connected to source (11). A floating gate (13) includes a tunnel-window section. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the source (11) and drain (12) regions, such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch).

Abstract: Reduced soft errors in charge-sensitive circuit elements such as volatile memory cells 200 occur by using boron-11 to the exclusion of boron-10 or essentially free of boron-10 in borosilicate glass 230, 240 deposited on the substrate 206 directly over the arrays of memory cells. Boron-10 exhibits a high likelihood of fission to release a 1.47 MeV alpha particle upon capture of a naturally occurring cosmic ray neutron. This capture occurs frequently in boron-10 because of its high neutron capture cross-section. Boron-11 does not fission.

Abstract: In a lead on chip, LOC, integrated circuit packaging arrangement, the conductors terminate in fingers that receive the bond wires. Adjacent the fingers, the conductors have arm parts extending over the major face of the integrated circuit. These arm parts are formed by stamping, rolling or otherwise to present an upwardly opening channel with at least the bottom lateral margins of the arm part raised above the plane of the bottom surface of the arm part. This reduces sagging of the arm part and capacitive interaction with the integrated circuit.

Abstract: A method for fabricating and for blowing top lead fuses (41 and 42) includes the steps of: (a) forming a conductive top lead fuse (41) on a layer of insulator (45); (b) depositing a layer of top insulator (47) over the top lead fuse at a top to sidewall thickness ratio of approximately 2:1; (c) anisotropically etching the top insulator back universally to a top to sidewall thickness ratio of approximately 1:2. The resulting top lead fuses (30 and 31) are selectively blown explosively out (24) of the top surface of the top insulator.

Abstract: The present invention is a programmable data processing system and apparatus which operates as an independent microprocessor. The programmable data processing system of the present invention stores both general purpose and special purpose graphic instructions. The programmable data processing apparatus of the present invention has both types of instructions within its instruction set. This provision of a single processing apparatus for preforming both types of instructions enables a highly flexible solution to bit map graphics problems. This is because the program of the data processing apparatus may be altered to provide the most desirable graphics algorithm without loss of the general purpose calculation and program flow capability of a general purpose data processor. The data processor of the present invention may serve as a parallel processor for a host data processing system for primarily control of bit mapped graphics.

Abstract: A method for estimating the shape of a body that emits electromagnetic energy using a sensor (10) having an image plane (15) and the ability to measure the intensity of the electromagnetic radiation (12) received at a point on image plane (15) comprises the steps of first expressing the intensity of radiation (12) reaching image plane (15) as a function of surface gradient parameters (p,q) for a pre-determined point (P.sub.i) on object (14). Next, the method requires measuring the intensity (E(s,t)) of radiation (12) that sensor (10) senses at the point (P.sub.i) on image plane (15). The method then requires determining the values of the surface gradient parameters (p,q) for the point (P.sub.i) on object (14) that minimizes the difference between the expressed intensity (F.sub.1 (p,q) for the pre-determined point (P.sub.i) on object (14) and the measured intensity (E(s,t)) at pixel (p.sub.i) on image plane (15).

Abstract: A method and apparatus (62) for processing images in symbolic space are disclosed. The method may include the steps of capturing a visual image (40), converting the visual image to a digital image (42), decomposing the digital image into image primitives (44), and processing the image primitives in symbolic space (46). The processing of the image primitives may include grouping the image primitives to form higher level image primitives, isolating portions of an image, filtering noise, identifying portions of an image, or adding to a knowledge base. The system or apparatus (62)for processing an image in symbolic space may include a camera (64), a video-to-digital converter (66), and a computer (68) with appropriate memory and software; the processing may include grouping the image primitives to form higher level image primitives, isolating portions of an image, filtering noise, identifying portions of an image, or adding to a knowledge base.

Abstract: The present invention includes a method of eliminating interference from an undersettled electrical signal, the undersettled electrical signal including a test signal at a known frequency. One embodiment of the present invention includes a method comprising the steps of providing a digitized version of the undersettled electrical signal (at 46); generating a frequency spectrum of the digitized version of the undersettled electrical signal (at 56); spectrally interpolating the frequency spectrum to generate an interference signal frequency spectrum (at 65); and subtracting the interference signal frequency spectrum (at 65) from the undersettled signal frequency spectrum (at 56) generating a settled signal spectrum (at 75).

Abstract: Memory cell transistors are provided in which column structures (12a, 14a) are formed at the face of a semiconductor substrate (10). Floating gates (46) and control gates (52) are formed adjacent to the column structures (12a, 14a). The floating gates (46) and control gates (52) are insulatively disposed by gate oxide layer (42) and insulating layer (50). Source regions (36) are implanted in the semiconductor substrate. Drain regions (38) are also implanted in the column structures (12a, 14a).

Abstract: A read/write memory is disclosed, which has the capability of writing the same data state to multiple memory cells in a selected row in a single cycle. The invention is incorporated into the memory by a capacitor which is selectively connected to one of the bit lines received by each sense amplifier to override the sensing operation, thereby setting the polarity of the sensed differential voltage to a predetermined state. The restoring operation of the sense amplifier restores the sensed data state into the selected memory cell, completing the write. The capacitor may be connectable to multiple bit lines, for efficiency of design. Each capacitor has sufficient capacitance to fully discharge a stored "1" value plus the dummy capacitor charge, for each of the bit lines to which it will be connected. Logic is incorporated into the memory to receive the data state to be written, and to receive the least significant bit of the row address.

Abstract: In accordance with one embodiment of the invention, a nonvolatile memory array is encased in a P-tank, and the P-tank encased in a deep N-tank, the two tanks separating the memory array from the substrate and from the other circuitry of the integrated memory circuit. The deep N-tank allows application of a negative voltage of perhaps -8 V to the P-tank encasing the memory array. Application of that negative voltage permits the cells of the memory array to be programmed with voltage pulses having a peak value of about +10 V, rather than the +18 V peak value of prior-art memory arrays. Because the external circuitry, such as the wordline driver circuit, need drive the wordlines at +10 V rather than +18 V, the invention permits construction of that external circuitry using thinner gate insulators and space-saving shorter dimensions.

Abstract: This is a method and system of extending the capability of a relational database management system's precompiler to object-oriented languages comprising: embedding SQL statement in an object-oriented program; compiling the object-oriented program with a precompiler from the database management system into a temporary file; compiling the temporary file with an object-oriented precompiler into a file acceptable to an object-oriented compiler; and compiling the file with the object-oriented compiler into an executable file.

Abstract: In a dynamic random access memory in which the number of data buffers is selectable, a buffer supply can be configured by a control signal to provide pump charge capacitance which is appropriate for providing the power required for energizing the selected number of buffers. In response to an external control signal, a second capacitor (or capacitor bank) can be precharged and then applied to the output terminal of buffer supply simultaneously with the precharging and application of the charge on the first capacitor. The dimension of the first capacitor is suitable for a buffer supply for the first buffer configuration and the second capacitor is suitable for a buffer supply for additional buffer amplifiers of the second configuration.

Abstract: A method and system are provided for indicating a change between a first image and a second image. In a first aspect, a sequence of images is sensed (304, 310) including the first and second image. The first image is previous in the sequence to the second image. Each image previous in the sequence to the second image is processed generating a first processed image (312). The first processed image and the second image are then processed generating a second processed image (316, 312). The first processed image and the second processed image are then processed generating an optical flow field (314). The optical flow field shows the change between the first image and the second image. In a second aspect, a first sequence of images including the first image is sensed (206). A second sequence of images including the second image is sensed (206). The first sequence is processed generating a first processed image (210). The second sequence is also processed generating a second processed image (208).

Abstract: A method for erasing blocks of a non-volatile memory includes detecting whether a block is in at least one of an erased state or a state secured from erasure; then setting a flag register at a first level for each block detected to be in at least one of an erased state or a state secured from erasure or at a second level for each block not so detected; then selecting for erasure blocks that have their respective flags set at the second level; and then erasing the selected blocks.

Abstract: The memory control this invention includes a microprogram-read-only-memory (CROM) containing micro instructions for operation of an integrated-circuit memory, a program counter multiplexer (PCM) to select instructions from the control-read-only-memory, a micro-instruction decoder (MID), a test input multiplexer (TIM) to test control signals, an optional status output register (SOR) to generate control signals, and an optional subroutine stack (SS) to allow function calls. Complex program, erase, and compaction instructions for the integrated-circuit memory are implemented using a relatively small number of control-read-only-memory locations and using a relatively small surface area on the memory chip. Control instructions are easily modified to compensate for process and structure enhancements are made during the production lifetime of an integrated-circuit memory.

Abstract: The invention provides an apparatus (10) for encasing a printed wiring board (12). Apparatus (10) comprises a substantially tubular housing (14) having internal ribs (30) formed along first and second sides (32) and (34) of housing (14). Printed wiring board (12) is received in housing (14) and maintained in place by ribs (30). An end cap (18) having an aligning member (36) is placed in a first opening (22) of housing (14). A coupling member (20) comprising a connector (40) and a support shell (42) is inserted into a second opening (28) of housing (14).

Abstract: A new signal quantization scheme is proposed which reduces fluctuation of the output signal by a signal quantizer (10) providing a quantized output signal and multiplying(18) said input signal X by a factor (1-w.sub.1)and finding a difference signal .DELTA..sub.n (11) between both the input signal and the previous input signal and multiplying (16) that by a weighting factor w.sub.2 from a control (13). The previous quantizer output signal Q.sub.prev is summed (17) with the weighted difference signal .DELTA..sub.in w.sub.2 and the sum is weighted by a weighting factor w.sub.1 at a multiplier (19) to yield w.sub.1 (Q.sub.prev +w.sub.2 .DELTA..sub.in). This signal is then summed at an adder (21) and applied to the quantizer (10) so that the quantizer is forced to match the fluctuation in the input signal as well as the signal itself. When applied to speech encoding algorithms such as the North American digital cellular telephone standard VSELP, the new quantizer results in more natural sounding background noise.