Abstract: The disclosure relates to a logic circuit wherein the voltage regulators of the ECL circuits, which use resistor ratios, the values of which are difficult to control in the formation of semiconductor circuits, are replaced by a series of diodes, the areas of which are very easy to control in semiconductor fabrication, to set the threshold voltages for the transistors. Diode voltage ratios are very controllable since the diodes change only about 18 millivolts for every factor of two in current change. Thresholds can therefore easily be set in five and ten millivolt increments, this being the procedure utilized herein. Embodiments are disclosed using the basic circuit in a stacked configuration to provide AND/NAND operation in addition to the OR/NOR operation of the basic embodiment.

Abstract: A bit slice processor system includes a bit slice ALU that is cascadable to provide multiple length words. Each of the ALUs provides both command outputs and status outputs. The status outputs are interfaced with each of the package as are the command outputs. Each of the ALUs in the cascaded ALU are controlled by an instruction word to perform a predetermined processing function. Internal status information is processed to generate a command output and a status output. This command is transmitted simultaneously with the status to the remaining packages in the cascaded array to provide processing control.

Abstract: A method of forming double polysilicon contacts to underlying diffused regions of a semiconductor body which includes forming first and second level electrically conductive silicon layers over the body which contact respective first and second diffused regions of the body. The diffused regions are formed such that said first diffused region is ringed by said second diffused region. The second silicon layer thus overlaps the first silicon layer. The top surfaces of the first and second silicon layers are silicided such that the silicide formed over the first silicon layer is aligned with the edge of the second silicon layer.

Abstract: A process for forming shallow silicided junctions includes the step of sputtering a layer of titanium (28) over a moat region to cover a gate electrode (18) and a sidewall oxide (22) formed on the sidewalls of the gate electrode (18). The titanium is reacted with exposed silicon regions (24) and (26) to form silicide layers (30) and (32) and then dopant impurities are implanted into the substrate (10) prior to stripping the unreacted titanium. The unreacted titanium (36), (38), or (40) functions as a mask to both offset the implanted regions from the channel region (20) under the gate electrode (18) and also to prevent impurities from entering the substrate at regions outside the defined moat region.

Abstract: One embodiment of the present invention includes a vertical inverter. A layer of P-type material is formed on the surface of an N+-type substrate, followed by formation of an N+ layer, a P+ layer, an N- layer and a P+ layer. (Of course different doping configurations may be used and remain within the scope of the invention.) A trench is then etched along one side of the stack thus formed and a connector is formed to the middle P+ and N+ layers. Another trench is then formed where a gate insulator and a- gate are formed. The gate serves as the gate for both the N-channel and P-channel transistors thus formed.

Abstract: The disclosure relates to integrated circuit resistors and matched resistor pairs wherein each resistor is split into plural segments, each segment having a separate field plate thereover, each segment having the field plate associated therewith connected to the non-common node thereof. In the case of the matched resistor pair, the interconnections between the segment of each resistor overlap. The segments are preferably substantially rectangular in shape with the major axes of all segments parallel to each other.

Abstract: The present invention provides a method, and a product made by the same, of fabricating an NPN bipolar transistor of a novel design simultaneously with the fabrication of double polysilicon CMOS/FAMOS devices, on an integrated circuit device. N wells 14 and 16 for the NPN transistor and the PMOS device are fabricated simultaneously. P type material is implanted to form the voltage adjust implant layer 19 of the FAMOS structure, and the base layer 18 of the NPN bipolar transistor, in the same process steps. In the process steps of forming the floating gate structure 36 of the FAMOS transistor, a polysilicon region 34 is also formed on the NPN transistor site. This polysilicon region 34 serves as a self-aligned implant mask during the implant of the base regions 88 of the NPN transistor. N type material is implanted in the same process steps to form the source and drain regions 66 of the FAMOS transistor and the emitter region 64 of the NPN transistor.

Abstract: The present invention teaches a process for fabrication of quantum-well devices, in which the quantum-wells are configured as small islands of GaAs in an AlGaAs matrix. Typically these islands are roughly cubic, with dimensions of about 100 Angstroms per side. To fabricate these, an n- on n+ epitaxial GaAs structure is grown, and then is etched to an e-beam defined patterned twice, and AlGaAs is epitaxially regrown each time. This defines the quantum wells of GaAs in the AlGaAs matrix, and output contacts are then easily formed.

Abstract: The disclosure relates to a shottky transistor logic (STL) exclusive-OR circuit with a buffer wherein the gate portion uses a pair of shottky clamp transistors having the base electrode of each cross coupled to the emitter of the other transistor through a schottky diode. Provision is made to provide and AND function at the input by providing plural emitters, each coupled to a separate input, on one of the transistors. A buffer circuit is provided to assit in operation at two volts rather than five volts.

Abstract: An infrared imager, wherein a transparent gate 14 is separated from a very narrow bandgap semiconductor 106 (such as HgCdTe) by a thin dielectric 15, 62. The gate 14 is biased to create a depletion well in the semiconductor 106, and photo-generated carriers are collected in the well. The gate voltage is sensed to measure the accumulated charge. Preferably the accumulated charge is not sensed directly from the gate, but the gate output is repeatedly averaged with another capacitor, so that the output of the imager is sensed as in average over a number of read cycles, which provides a greatly improved signal-to-noise ratio. Preferably an array of the MIS detection devices is formed in a thin layer of HgCdTe 106, which is bonded to a silicon substrate 107 containing a corresponding array of the averaging capacitors with addressing and output connections, and via holes 16 through the HgCdTe are used to connect each detection device to its corresponding averaging capacitor.

Abstract: A method and apparatus is provided for removing submicron sized particles from the surface of a silicon semiconductor wafer (38). Conventional cleaning methods are capable of only removing particles that are about 1 micron or larger in size. The present invention provides a way to increase the submicron particles in size so that they are removable by the known methods. The silicon semiconductor wafer (38) is cooled by a refrigeration unit (36) or by exposure to liquid nitrogen (74). The cooled wafer (38) is then exposed to a condensable material (42) which is allowed to condense on the surface of the wafer (38). The condensable material will surround any particles that are on the surface and cause them to grow in size due to the formation of frozen crystals. Without allowing the crystals to melt, the enlarged particles then are removed by any of the known methods.

Abstract: A method for forming CMOS device wherein the NMOS devices are bulk devices and the PMOS devices are SOI devices. The PMOS devices are formed with their channel regions in a silicon-on-insulator layer, preferably a laterally recrystallized annealed-polysilicon layer over a silicon dioxide layer.

Abstract: A method for forming a BICMOS device having MOS devices and bipolar devices formed during the same process includes the step of first forming bipolar MOS regions and then forming gate electrodes in the MOS regions and poly emitters in the bipolar regions. The gate electrodes and bipolar regions have a layer of refractory metal formed on the upper surface thereof and covered by a protective cap. The extrinsic bases formed on either side of the emitter electrode and the source/drain regions are formed on either side of the gate electrode by forming a layer of silicide and implanting the layer of silicide with p-type impurities which are subsequently driven downward into the substrate. The protective cap prevents the p-type impurities from being introduced into the poly emitter.

Abstract: Disclosed is a small-area solid state driver (30) adapted for switching high voltages. The driver (30) includes a DMOS device (48) driving a bipolar SCR (58). A SCR NPN transistor (54) and PNP transistor (56) are parasitic in nature, thus reducing the wafer area of the driver (30). The SCR (58) provides current sink capabilities to the driver output (60). Current source capabilities are provided by a substrate input terminal (50) which is connected to the output (60) by diodes (84, 86). A third input (52) allows the SCR (58) to be disabled.

Abstract: The present invention relates to a bilayer photoresist process, wherein a first planarizing resist layer is applied to a base and a second or top photoresist layer is applied over the first. The top layer resist is sensitive to deep UV light, while the planarizing layer resist is sensitive to near UV or violet light. The top layer, by use of a dye or other means, is opaque to predetermined near UV or violet wavelengths by which the planarizing layer is illuminated. The top layer is patterned using deep UV light. A flood exposure of the predetermined near UV or violet wavelengths is then used to transfer the pattern of the top layer to the bottom planarizing resist layer. Improved resolution is achieved by the use of deep UV light for patterning the top layer. Less costly yet faster illumination of the planarizing layer is accomplished by using near UV or violet light. Additionally pattern degradation due to spurious reflections normally occurring from near UV exposure of the top layer is avoided.

Abstract: Noise and fault tolerant devices made of cellular automata are disclosed. Preferred embodiments include cellular automata with updating rules that set a cell to a first state if more than a threshold number of adjacent cells are in the first state and with output being a state average over all cells; thus updating overcomes noise and fault induced state changes. Embodiments with cells as discrete electronic devices and with cells as quantum wells in a monolithic semiconductor body are disclosed.

Abstract: A solder paste mixture for soldering surface mount devices to a circuit board using a reflow soldering process which utilizes a vapor phase furnace. The solder paste mixture has a metallic content which is 63% tin and 37% lead. The metallic content of the paste consists of 150 micron particles of 100% tin and 150 micron particles of an alloy of 10% tin and 90% lead. Included in the process of soldering components to the circuit board is the step of prebaking the circuit board with solder paste and components in their proper place on the board.

Abstract: A voltage controlled oscillator circuit of a type having a tank circuit for generating oscillations which includes a means for establishing a fixed bias voltage with respect to ground at a bias end of said tank circuit, means for drawing current from an a.c. end of said tank so as to control the tank gain, and an AGC capacitor. A constant current source is coupled to the AGC capacitor for supplying it with a constant charging current. Means are provided for discharging the AGC capacitor at a voltage level determined by a ratio of resistors and a transistor emitter-base ratio.

Abstract: A non-volatile memory wherein the channel of the floating gate memory devices is recessed.

Abstract: A push-push broadband dielectric resonator oscillator circuit that operates in the K and Ka band frequency range has two oscillator circuits that oscillate at the same fundamental frequency. An antiphaseal relationship is maintained between the two oscillators through the use of a dielectric resonator and the desired frequency is obtained by vectorially combining the output signals of the two oscillators that have the antiphase relationship to obtain an output frequency that is twice the fundamental frequency of operation of each of the individual dielectric resonator oscillator circuits.