Abstract: Metal contacts and interconnections for integrated circuits utilize copper as the primary conductor, with the copper being totally encased in refractory metal layers on both top and bottom surfaces and also sidewalls. The contact hole in silicon oxide may be filled with a plug of refractory metal before the copper is deposited, or the first refractory metal layer may be conformally deposited to coat the sidewalls of the hole.

Abstract: A multiple recess isolation technology avoids stress induced defects while providing a substantially planar surface. A silicon substrate (10) is patterned and etched, creating active moat regions (18) and recesses (20a-b and 21a-b). The recesses are filled with oxide by growing a field oxide (40) in wide recessed regions (21) using a LOCOS process, while depositing a planarization field oxide (44) in narrow recessed regions (20). After etching the structure to obtain a planar surface, standard procedures are used to fabricate the active devices. The process uses a single photolithographic masking step and results in only a very small loss of the width electrically active regions.

Abstract: A cascadable first-in, first-out memory unit (11, 12, 13) has a load/unload control (152) for write-addressing and read-addressing selected memory locations within its memory array (82). A write pointer (110, 112, 120) keeps track of the number of write operations that have occurred in the selected memory unit, and a read pointer (130, 132, 142) does the same for the number of read operations. When the number of write operations performed since a last reset pulse (416) equals the number of memory locations in the memory array (82), write control passes to the next succeeding FIFO memory unit by a descending transition of an output control signal (444). Read control is passed to the subsequent FIFO by an ascending transition (470) of the same output control signal.

Abstract: Disclosed is a supply voltage monitor for detecting the asymmetric decay of one voltage source (V.sub.dd) with respect to another voltage source (V.sub.ss). The monitor circuit (24) includes a resistive voltage divider (26) having a plurality of voltage tap positions (32,35,38). A sensor transistor (40) monitors the voltage between a common connection (16) connecting the voltage sources and the voltage at a desired tap position (38) of the divider network (26). On detecting an imbalance between the voltage sources (V.sub.dd, V.sub.ss), the sensor transistor (40) drives a current mirror circuit (42). The current mirror circuit (42) defines an output (50) of the monitor circuit (24), together with a reference transistor (48) biased by a voltage of the divider network (26).

Abstract: The disclosure relates to a circuit for compensation for ground glitches in an integrated circuit wherein there is provided a glitch fix circuit wherein a node is responsive to a negative shift in the level of ground relative to Vcc to turn on a transistor and drain current to ground from the input circuits to transistors in the circuit under control. A feedback circuit is provided which is out of phase with the circuit input of the circuit being controlled and which is one Von above ground. This feedback circuit inhibits the glitch fix circuit in the event that the increase in voltage difference between the input to the circuit being protected and ground is a result of a high input signal rather than noise which lowers the ground level.

Abstract: A self-aligned, single polysilicon transistor is fabricated using nitride spacers (26, 68) to self-align the extrinsic base regions ( 48,80). The space between the base contacts (36,76) and the emitter contacts (34,78) is defined by the width of the nitride spacer plug (26,68) less the oxide encroachment from a thermal oxidation of the underlying polysilicon.

Abstract: An X-cell EEPROM array includes a plurality of common source regions (50) that each border on four gate regions (46), both formed at a face of a semiconductor substrate (10). Each gate region (46) further adjoins a common drain region (52). Each drain region (52) is a common drain for two EEPROM select and memory transistors. A common erase region (54) is implanted into the semiconductor layer (10) in a position remote from the source regions (50) and the drain regions (52). Four floating gate electrodes (40) extend over tunnel windows (22) that are formed on the semiconductor layer (10) in positions adjacent a single erase region (54). An integral contact (64) is made through multilevel oxide (56, 58) from a metal erase line (70) to each erase region (54).

Abstract: A solid state memory system is arranged in a plurality of blocks of memory cells, the memory cells in each block arranged in columns and rows. When the memory system is addressed for a memory reference, block selection circuitry selects one block of the plurality of blocks, excluding all of the other blocks. Each block has a set of sense amplifiers, corresponding in number to the number of bits in the output word. Each sense amplifier is connected to an isolation switch. The outputs from the sense amplifiers connected to the non-selected blocks are thereby isolated from the sense amplifier outputs from the selected block to minimize loading of the sense amplifier outputs from the selected block. The memory cells in each block are interconnected by metal row conductors and by metal column conductors.

Abstract: A microsequencer includes a memory array (110) which is interfaced with a push/pop register (100). Data is input to the push/pop register (100) through a multiplexer (104) and also to Read register (102). The stack comprised of the RAM (110) and the register (100) can be push or pop with control logic (120). Stack pointer (130) and Read pointer (134) are provided for storing the stack and read pointers. The Read register (102) allows reading of data independent of the contents of the push/pop register (100) and the Read pointer (134) allows independent reading of information in the RAM (110).

Abstract: A method of forming trench isolation is disclosed. A trench is etched, either through field oxide or not, into the substrate, using an oxide hard mask. Implant of a channel-stop is then performed through a dummy sidewall oxide, followed by stripping of the dummy oxide and regrowth of the sidewall oxide. A polysilicon layer is deposited into the trench and over the wafer, and is etched to clear from the surface, and overetched so that a recess is formed within the trench. The recess is then filled with a TEOS oxide layer deposited over the wafer surface, and the deposited oxide at the top of the trench is planarized with the surrounding surface.

Abstract: A cursor control system for computer displays moves a cursor unambiguously in three dimensions using a two dimensional input device. The plane of movement of the two dimensional device is divided into logical regions which correspond to movement along a three dimensional axis. Movement of the two dimensional device into one of these regions causes the cursor to move along the corresponding axis of the display.

Abstract: The preferred embodiments include Schottky barrier diode (80) clmaped bipolar transistors for use in planar integrated circuits with the diode (80) being formed in a trench to increase junction area, reduce series resistance from junction to the buried layer (64), and reduce lateral extent of the extrinsic base (78).

Abstract: The invention provides an EPROM having a high quality dielectric to separate the floating gate from low quality dielectric layers used in the prior art by the method outlined as follows. First, the polycrystalline silicon floating gates are formed and partially patterned on the surface of a substrate. A thin thermally grown oxide layer is then formed over the entire array. The source/drain regions are then implanted through the thin silicon dioxide layer into the substrate. Next a thick silicon dioxide layer is deposited by chemical vapor deposition on the surface of the array. The surface of the array is then coated with photoresist which, because of its nature, provides a planarized surface on the top layer of photoresist. The photoresist and the silicon dioxide layer are then etched using an etching process which provides an etching ratio of 1:1 between photoresist and silicon dioxide. The photoresist is completely etched away thus leaving the planarized silicon dioxide surface.

Abstract: A DTMF receiver (10) recognizes each of a plurality of multi-frequency tones, each tone centered on a predetermined standard frequency. Two digital bandpass filters (14, 16) each have four frequency bins, each frequency bin operating according to a recursive second-order transfer function for preferentially transmitting frequencies near the standard frequencies. Each frequency bin accumulates, for each of a plurality of sampling periods, respective spectral energy signals from the input signal. A temporal energy signal is derived from the spectral energy signals. For each bandpass filter (14, 16), a time-domain test template generator (30) and a frequency-domain test template generator (34) are provided to generate time-domain and frequency-domain test templates. These test templates are input to an analyzer (38) that compares the templates against data-adaptive frequency-domain and time-domain reference templates.

Abstract: A memory cell (10) comprises a ferromagnetic gate (12) disposed above a source (18) and a drain (20) in a substrate (16). A magnetic field is created in the ferromagnetic gate (12) by producing a large current between the source (18 ) and drain (20). The orientation of the magnetic field will depend upon the direction of the current flow. To read information from the memory cell (10), a small current is passed from source (18) to drain (20); if the electrons (25) are deflected upwards towards the surface (24) of the substrate (16), a lesser current will result than if the electrons (25) are deflected downward towards the bottom of the channel (22). Hence, the magnetic orientation, and therefore the information stored within the memory cell (10), can be determined by the amount of current detected.

Abstract: The disclosure relates to a cache memory formed on a single chip wherein the ability to test the address comparator, cache memory diagnostics are improved, cache memory are capable of being read out. The architecture comprises a parity generator, a parity checker, a comparator and an SRAM memory cell array. The cache memory is cascadable for access to an increased address range and to provide increased memory capacity.

Abstract: The present invention provides a structure and method for fabricating that structure which provides increased capacitance over the prior art while occupying a minimum of surface area of the integrated circuit. The present invention accomplishes this by interleaving multiple capacitor plates to provide increased capacitance while occupying the same surface area as a prior art capacitor providing a fraction of the capacitance provided by the present invention. The present invention is fabricated by providing a capacitor stack which includes interleaved plates of material which may be selectively etched and which is separated by appropriate dielectric material. One portion of the stack is masked while one set of the interleave plates is etched. The etched portion of the interleave plates is filled by a suitable dielectric and a contact is made to the remaining plates. A different portion of the stack is then exposed to an etch which etches the other set of interleave plates.

Abstract: The disclosure relates to a method for low temperature (less than 120 degrees C.) hardening of photoresist pattern by providing a high power light beam consisting of light having a wavelength of about 300 nanometers and above which leads to crosslinking throughout the resist. A hot plate constant temperature (less than 120 degrees C.) is optionally used to accelerate the crosslinking reaction, thus incrasing throughput.

Abstract: Disclosed is a bipolar-CMOS circuit which includes a NMOS transistor site (18) electrically isolated from a bipolar transistor site (16). The NMOS transistor site (18) includes a semiconductor region (24) isolated from a bipolar transistor well (26) by deep diffusion ring (32). A buried layer (13) forms a bottom of the deep diffusion isolation ring (32). A backgate voltage can be applied to the isolated semiconductor region (24) of the NMOS device, which bias may be different than that applied to the substrate (10). Optimum performance of the NMOS transistor is thus assured irrespective of the magnitude of operating voltage of the bipolar transistor.

Abstract: A bipolar-CMOS static random access memory device which includes a plurality of static random access memory cells arranged in columns and rows, complementary pairs of bit lines coupled to the cells in each row, word lines coupled to the cells in each row of the cells and a plurality of sense amplifiers and write circuits, with a separate sense amplifier and write circuit coupled to each pair of the complementary bit lines.