Abstract: A BiCMOS static random access memory (SRAM) is disclosed, which has first and second stage sense amplifiers. Each column in the memory array is associated with a first stage sense amplifier, and the first stage sense amplifiers are arranged in groups, with each group connected in wired-AND fashion to a pair of local data lines. The column address is used to select one of the first stage sense amplifiers for sensing the state of the memory cell in the selected column. One second stage sense amplifier is associated with each group of first stage sense amplifiers, and the second stage sense amplifier associated with the group containing the selected first stage sense amplifier is selected, according to the most significant bits of the column address. The second stage sense amplifiers are connected to a data-out bus in wired-OR fashion, with the output of the selected second stage sense amplifier driving the data-out bus.

Abstract: High current capacity output drivers for digital devices have output noise reduced and more quickly achieve stability by the insertion of resistance in series with inherent, parasitic inductance. The resistance may be one or more fixed resistances formed in the same circuit as the drivers. The resistance may also include sensor devices that selectively increase the resistance of the output drivers in accordance with the voltage produced by the parasitic inductors. Both fixed resistances and sensor devices may be used together.

Abstract: Laser (12) assisted photochemical etching of Hg.sub.1-x Cd.sub.x Te-type compounds (30) in solutions of bromine and other oxidants.

Abstract: A circuit for resetting a multi-bit word in a digital memory at a selected address receives a word reset signal to cause entry into the selected address of a multi-bit word wherein all the bits are set to the same level and a parity bit is set to a value corresponding to parity in the multi-bit word. The circuit includes a parity generator which receives a multi-bit input data word and generates at least one parity bit therefrom. During a normal write operation, the multi-bit input data word and the parity bit are written into the digital memory at the selected address. During a word reset signal, output from the parity generator and the multi-bit input data word are blocked from entry into the memory.

Abstract: Multichannel interconnection networks with optical deformable mirror devices as the reconfigurable switching element.

Abstract: A method of forming thin epitaxial layers by subjecting a substrate to a high temperature prebake followed by a medium temperature capping seal and a low temperature deposition is disclosed. In a preferred embodiment the epitaxial layer is formed by low pressure chemical vapor deposition of dichlorosilane. The method has been demonstrated to alleviate the increase in autodoping and epitaxial defects normally associated with lowering the deposition temperature.

Abstract: Test logic may be included in the design of an integrated circuit (IC) to facilitate testability. In most instances, an IC's test logic can only be activated while the IC, or logic sections within the IC, are placed in a non-functional test mode. The present invention is directed toward an event qualification structure providing the timing and control required to activate an IC's test logic during normal functional operation.

Abstract: A programmable sequence generator comprises a combinatorial logic matrix (10,12) and an on-chip timer (24) having count lines (26) coupled as inputs to the logic matrix (10). Combinatorial logic functions may be programmed into the matrix having as variables external inputs (14), a count number represented by the count lines (26) and internal inputs (48) fed back from outputs of the logic matrix (12). In a preferred embodiment, state registers (46) are provided, such that the programmable sequence generator can operate in any one of a plurality of different states. The programmable sequence generator can be configured as a waveform generator (92), a refresh timer (94) or a dynamic memory timing controller (96), among other programmable logic applications.

Abstract: A hybrid ECL memory includes a hybrid memory array 36 which utilizes cross coupled CMOS latches (70). Each CMOS latch (70) is accessed by an ECL decoder (40) and an ECL Word Line driver (42) to read data therefrom. Data is accessed through a bipolar transistor (120) for output to an ECL sense amp. The column select operation is provided by an ECL decoder (50) to select both the Read and the Write operation. The Write operation is provided with emitter coupled logic by pulling up one of the storage nodes in the CMOS latch (70) with a low source impedance PNP transistor (122). Selection is provided by varying the Word Line between two voltages through a low source impedance transistor (78) with the voltages being ECL compatible.

Abstract: A semiconductor memory includes a memory cell (42) which utilizes a cross-coupled bipolar SCR latch. The latch includes two sense nodes (78) and (80). Sense node (78) has associated therewith an NPN transistor (82) and a PNP load transistor (84). Similarly, sense node (80) has associated therewith an NPN transistor (90) and a PNP load transistor (92) configured as an SCR. Each of these sense nodes is cross-coupled to the base of the NPN transistor connected to the opposite sense node. A forward biased PN junction is connected between an external Write circuit and the collector of each of the NPN transistors to provide an independent current path when changing from a low logic state to a high logic state. This decreases the recovery time when going from a saturated to a cut-off state for the NPN transistor.

Abstract: An analog interface system interfaces with a digital signal processor. The system receives analog signals, digitizes those signals and transmits them to the signal processor upon completion of the conversion. The system directs transmission of digital data from the signal processor to the system, and converts it to analog as the output of the system. The A-to-D and D-to-A conversion rates are selected by the system control, responsive to data received from the signal processor.

Abstract: A switchable gain circuit includes an operational amplifier (10) which has an input leg comprised of a series resistor (20) and an MOS transistor (22). A plurality of feedback legs are formed, each comprising one or more resistors that are equal in value to the input resistor (20), and connected in series with a switch transistor. The proportion of the series resistance of the transistor in a given feedback leg to the series resistance in the transistor in the input leg is equal to the proportion of the fixed resistance in the feedback leg and input leg. The value of the series resistance of the feedback transistors therefore factors out the series resistance of the input transistor (22) in the gain calculation. This significantly reduces harmonic distortion in the output signal.

Abstract: The disclosure relates to an STL flip flop circuit composed of a pair of latch circuits, the first latch circuit receiving R and S inputs and the clock signal and floating relative to the other latch circuit. The second latch circuit is referenced to ground and is driven by the output of the floating latch circuit. All components are of the schottky type, the semiconductor devices being schottky clamp transistors and the diodes being either TiW or PtSi type. In accordance with a second embodiment of the invention, a pair of inverter circuits are each coupled to the R and S inputs of the first embodiment, one of the inverters being controlled by an external data source, whereby, the inverters always each provide opposite outputs to the R and S inputs, depending upon the data input. Schottky clamp transistors and two different types of schottky diodes are utilized.

Abstract: Disclosed is a floating gate memory array having high-speed programming capabilities. Diffused buried bit lines (14) are formed spaced apart in a semiconductor, forming conduction channels therebetween. Dielectric-filled trenches (24) are formed between the bit lines (14). An insulated floating gate conductor (18) and an insulated control gate conductor (23) are formed over the wafer and patterned to extend over the dielectric-filled trenches (24). The enhanced coupling efficiency between the control gate (23) and the floating gate (18) enhances the programmability of the memory cells.

Abstract: A vertical PNP structure for use in a merged bipolar/CMOS technology has a P+ buried layer (84) as a collector region, which is isolated from the P substrate (48) by an N- buried layer (82). The P+ buried layer (84) diffuses downwards into the N- buried layer (82) and upwards into a P- epitaxy layer (52d) and into a base region (54c). The base region (54c) is formed in the same processing step as the N well region (54b) of the PMOS transistor (42) and the collection region (54a) of the NPN transistor (40). By diffusing into the base region (54c), the width between the collector (84) and emitter (64e) is reduced. The emitter (64e) can be formed in conjunction with the source and drain regions of the PMOS transistor (42).

Abstract: A digital crossbar switch for switching data from an input/output data bus to an internal data bus and to the same or another input/output data bus which includes a plurality of multiplexer logic units, an m-bit internal data bus coupled to each of said multiplexer logic units where m is an integer, and a plurality of n-bit input/output data buses one connected to each of the multiplexer logic units were n is an integer. The switch further includes an m/n to 1 multiplexer, where m/n is an integer, in each multiplexer logic unit. The m/n to 1 multiplexer has an input control to the internal data bus and an output coupled to a corresponding one of the input/output data buses and is operative in response to a configuration control signal to switch a selected n-bits of data from the internal data bus to the corresponding input/output data bus. A memory storage for storing configuration control signals is coupled to the m/n to 1 multiplexer.

Abstract: A content addressable memory consists of a plurality of memory units each of which may be an integrated circuit. Each unit receives an input group of digits forming all or part of an input key code, and compares it simultaneously with a plurality of equally sized groups of digits stored in the memory of the unit. The memory of a unit has 32K bytes of storage elements functionally arranged in 512 rows and column. The 64 bytes forming a row are each compared with an input group of 8 binary digits. A status bit is produced for each of the 64 bytes of a row and indicates whether or not the input group matches the particular byte. The match need not be perfect and certain digits may be masked so that comparison of them does not detract from the match assessment. The status bits are combined logically to produce higher and higher order status bits selectively indicating the presence of a match in larger and larger groups of storage elements up to the entire memory of the unit.

Abstract: A dual-slope A/D converter circuit has an oscillator (14) whose timing frequency is determined by the value of an oscillator resistor (70) and a oscillator capacitor (72). An integrator (66) integrates an input voltage at a rate determined by an integrating resistor (64) and an integrating capacitor (68). The oscillator resistor (70) and integrator resistor (64) are designed such that their ratio will remain constant despite variations in actual value due to manufacturing inaccuracies. The oscillator capacitor (72) and integrating capacitor (68) are similarly designed. Consequently, an optimum peak integration value can be obtained at full scale input despite variations in actual resistive and capacitive values.

Abstract: Polysilicon gate insulated gate field effect transistors with threshold adjustment implants made after the gate oxide (156) and a split of the polysilicon gate (158) have been formed provides a shallow, tight dopant profile.

Abstract: A via (64, 66, 68) comprises a conductor (45, 46, 48) having a first surface (58, 60, 62) and at least one second surface (49) that forms at least one edge (52) with the first surface (58, 60, 62). A first insulator layer (33) is formed on the first surface and defines a first area (58, 60, 62) on the conductor that is not covered by the first insulator layer (33). A second insulator layer (70) is formed over the second surface (49). The first and second insulator layers (33, 70) define a via (64, 66 and 68) to the conductor (45, 46, 48) . The bottom area (58, 60, 62) of the via (64, 66, 68) is equal to the first area and is bounded in part by the edge (52).

Abstract: A BiCMOS static random access memory (SRAM) is disclosed, which has first and second stage sense amplifiers. Each column in the memory array is associated with a first stage sense amplifier, and the first stage sense amplifiers are arranged in groups, with each group connected in wired-OR fashion to a pair of local data lines. The column address is used to select one of the first stage sense amplifiers for sensing the state of the memory cell in the selected column. One second stage sense amplifier is associated with each group of first stage sense amplifiers, and the second stage sense amplifier associated with the group containing the selected first stage sense amplifier is selected, according to the most significant bits of the column address. The second stage sense amplifiers are connected to a data-out bus in wired-OR fashion, with the output of the selected second stage sense amplifier driving the data-out bus.