Abstract: Incoming data in binary form is retimed, and under control of a framing clock, a first counter clocks in four bits in the first stage of a preview store; and a second counter clocks in eight bits, four bits in each of the second and third stage of the preview store. The first bit in each instance is the framing bit for the next previous frame location and the second next previous frame location so long as an in-frame condition exists, and the frame control is in synchronism with the framing bits contained in the incoming data.The current data bit is compared with the bits appearing at the output of the first and second stages of the preview store to determine if the three bits comprise a valid framing sequence for a non-winking framing sequence in which any combination of the following frame bit indications may occur-F1 F0 F0 F1-where the number following the F indicates the state of the framing bit.

Abstract: A linearity test signal generator alternately provides a burst of a modulation frequency and no modulation to the modulation input of the frequency modulator oscillator (FMO) under test. A programmable divider is connected to the output of said frequency modulated oscillator to produce a binary output signal which is applied to the automatic phase control circuit. This circuit in turn develops a DC control signal which is applied to the control input of said frequency modulated oscillator to maintain the average oscillator frequency constant. This DC control voltage gives an indication of the shift in the average free running frequency of the oscillator while being modulated, caused by oscillator non-linearity. The voltage is first sampled when the oscillator is unmodulated to produce a reference voltage which is stored and then compared to a sample of the DC control voltage when the oscillator is being modulated.

Abstract: An APC (automatic phase control) circuit is utilized to measure the linearity of an FMO (frequency modulated oscillator). In accordance with a common APC concept a programmable divider is connected to an output of said frequency modulatable oscillator to produce a binary output signal having a predetermined pulse repetition rate. This signal is compared with a reference oscillator signal in a phase control comparator producing a DC control signal which is applied to the control input of said frequency modulated oscillator to maintain the average oscillator frequency constant. This DC control voltage gives an indication of average free running frequency of the oscillator.To measure linearity, the said binary signal at the programmable divider output is also further divided and processed to produce a low frequency square waveform which is applied via a manual ON/OFF switch and a modulation amplifier to the modulation input of the said FMO.

Abstract: An input signal is applied to the inverting input of a class B amplifier and to the input of a limiter circuit. The square wave signal from the limiter is applied to the input of a switching amplifier which drives this amplifier between V and ground at the switching rate established by the input signal; thereby, obtaining a power control signal. The power control signal is applied to one terminal of a load and to the non-inverting input of said class B amplifier. Ignoring the input signal to the amplifier, this switches the output of the class B amplifier between V and ground at the same rate and in phase with the output from the switching amplifier. The gain of the input signal path in the amplifier is such that the input signal will just drive the output between V and ground. The switching action of the power control signal in combination with the input signal then causes the output signal across the load to have the same characteristic as the input signal but with a peak-to-peak amplitude of 2V.

Abstract: A carrying case or portable pack is constructed in the form of an attache case. A tray storage area providing receptacles for separately holding relatively long and narrow objects is releasably attachable to the inner surface of the lid and flat bulk storage is provided between the base of the tray and said inner surface. A holding material is attached along the inner side walls of the base and individual pockets, for separate package storage, have a surface material mounted on the exterior thereof which permits releasable attachment to said holding material. The pouches or pockets may vary in size, thus permitting flexibility in storing the packaged materials. In addition, the pouches may be coded, as by color coding, for rapid identification and selection of items to be used for a particular function, for example in a medical procedure.

Abstract: One or a burst of error signals from an error detector are applied to one input of a latch. The first error received during a "window" forces the latch to a set position, and a subsequent enabling pulse reads the error occurrence into the count up input of an up-down counter. Following the enable pulse, the latch is reset. If one or more errors occur during the subsequent window period, another error occurrence is read into the count up input. Otherwise, the occurrence of the enable pulse reads the absence of an error into the down count input of said up-down counter. On a full count, an output latch circuit is set by an output signal from the counter. The latch is not reset until a zero count is obtained in the up-down counter. Overflow and underflow are prohibited by circuits external to the up-down counter.

Abstract: In a microstrip frequency modulated oscillator, the linearity of the modulating circuit incorporating a varactor diode is adjusted by using a microstrip transmission line as a secondary resonator in conjuction with a variable reactor. The varactor is connected to one end of this resonator which end is also connected to the main resonator of the microstrip oscillator. The variable reactor is connected between the other end of the secondary resonator and ground.

Abstract: A 70.+-..DELTA.f MHz sinusoidal test signal from a standard radio link test set is down converted and shaped to obtain a 35.+-..DELTA.f/2 MHz sinusoidal test signal to be applied to the radio set under test. The output of the radio set is applied to an up converter in which a multiplier is used that maintains the amplitude information as it doubles the frequency. The 70.+-..DELTA.f MHz test signal from the up converter is then applied to the input of the radio link test set, and the characteristic is measured as if the radio set under test employed a 70 MHz IF, rather than a 35 MHz IF.

Abstract: The baseband input to a frequency modulation radio transmitter is switchably connectable to a square wave generator, the amplitude of the square wave output being adjusted to provide a predetermined deviation of the FM radio transmitter. The output frequency of a pilot oscillator is also applied to the baseband input and is subjected to amplitude modulation because of non-linearities which exist in the system and which adversely affect the signal during transmission through the system.At the receiving end of the radio system, the receiver output contains a signal comprising the pilot frequency and a superimposed amplitude modulated signal, and this signal is applied to a product detector. The output of the product detector is a pulsating DC signal comprising a basic DC component, which is representative of the amplitude of the pilot frequency, and an AC component, which is representative of the system non-linearity. The pulsating DC signal is applied to one terminal of a capacitor.

Abstract: The baseband input to a frequency modulation transmitter is switchably connectable to a square wave generator, the amplitude of the square wave output being adjusted to provide a predetermined deviation of the FM radio transmitter. The output frequency of a pilot oscillator is also applied to the baseband input and it is subjected to phase modulation because of group delay which exists in the system and which adversely affects the signal during transmission through the system.At the receiving end of the radio system, the receiver output obtains the pilot signal which has been phase modulated by the group delay slope in the system, because of the square wave test signal. This phase modulation is detected in a phase lock loop, amplified, rectified and applied to a meter so as to provide an indication of the group delay slope in the system.

Abstract: First and second NPN transistors are direct connected in an astable multivibrator configuration. Each collector is connected to the positive terminal of a DC power source through series connected diodes. A resistor, which is selected to control the amplitude of oscillation, is connected between the collectors. The frequency of oscillation is controlled by a frequency determining component which is connected between the emitters of said transistors. The emitters are connected to current sources.

Abstract: An inverter accepts the true form of a high-frequency signal at its input and provides the complement thereof at its output. The true form is applied to a first input of a first NAND-gate and the complementary form is applied to a first input of a second NAND-gate. A second signal, having a repetition rate which is set, for example, by the channel spacing required in an FDM carrier system, is applied to the second inputs of said first and second NAND-gates. The second signal is thereby alternately switched between the first and second output terminals of said NAND-gates at a rate equal to the frequency of the high-frequency signal. The first and second output terminals of said NAND-gates are connected to the first and second end terminals, respectively, of the primary winding of an output transformer. The end terminals of the secondary winding of said transformer are connected to the load or utilization device. The output signal comprises a spectrum having a sin x/x envelope centered at the high-frequency w.

Abstract: A switched mode power supply employs a pulse width modulation controlled DC-to-DC converter to change a first voltage from a source of DC power into a regulated power source providing direct current at a second DC voltage. A transformerless current-sensing device is adapted for connection in the path between said source and said converter and provides a control signal which is representative of the current flowing in said path. A current-limiter control circuit is responsive to said control signal and provides an enabling output state when the sensed-current exceeds a predetermined value. The enabling state overrides the pulse width modulator control and inhibits the converter, thus terminating the output pulse when the sensed current exceeds said predetermined value.

Abstract: An active filter used for the loop filter of a phase-lock loop has one input to the operational amplifier thereof connected to receive the output from a phase detector, and has the non-inverting input connected to receive a control signal from an override signal generator. Under normal operating conditions, the output from the override signal generator is such that it does not affect operation of the active filter and the filter operates as a standard loop filter. During abnormal operating conditions the output signal from the override signal generator is of such magnitude that it causes the operational amplifier and, hence, the filter to output the maximum voltage +V. The filter output is connected to one end of a pair of serially connected resistors which have the node connected to the control voltage input of the voltage control oscillator. The other end of the serially connected resistors is connected to the collector of a transistor.

Abstract: Finger prints of authorized personnel are initially stored in digital form in a memory. Subsequently, personal identification is obtained by matching the fingerprints of individuals with the stored prints. The individual places his finger in an activator which indexes the finger and turns on the equipment. The fingerprint image may be refleted directly into an electronic image sensor or it may be initially impressed upon a tape for later image scanning. In either case, the electronic image sensor scans the fingerprint image and converts the optical characteristic of the print into a plurality of picture elements, and provides an electrical signal representative of each of the picture elements at its output. The picture elements are converted either in the electronic image sensor or in an analog to digital converter into a digital code representative of each picture element. These digital codes are entered into a temporary storage for comparison with the fingerprints contained in the memory.

Abstract: A network simulating an ungrounded inductor includes an active gyrator circuit which employs an operational amplifier, said gyrator being a two port device having an ungrounded port, and a grounded port. The ungrounded port is terminated in a capacitor C so as to provide an input impedance, Zin, looking into the grounded port, which simulates an inductor: Zin=e1/i1=j.omega.R.sup.2 C, where .omega.=2.pi.f, e1 the voltage across the port and i1 is the current into the port. A current i2 is developed in the gyrator circuit, from the operational amplifier output, and appears as an extraneous current at the grounded terminal of the grounded port. An active network including a second operational amplifier is connected to the active gyrator circuit and is arranged to provide a current i3 which is equal in value to but opposite in sign from said i2 current. The current i3 is combined with the i1 and i2 currents at the grounded terminal.

Abstract: Operating power for line signal repeaters is fed over a transmission cable pair (signal line) which is susceptible to lightning strikes and, thus, to longitudinally induced currents in the DC power feed circuit. A symmetrical non-linear power regulator is connected between the signal line and the line signal repeater, and includes a high current shunt regulator which bypasses excessive induced currents. By so doing the adverse effects of these induced currents on the operation of the line signal repeater is minimized. A shunt voltage regulator provides the line repeater with a constant operating voltage when the line current (DC line power feed current plus induced currents) is greater than the minimum required bias current. When the potential at input terminals of the power regulator exceeds a predetermined value, a portion of the excess current is conducted through a blocking diode to charge an energy storage device.

Abstract: An error detector provides an output pulse whenever an error is detected in the framing pattern of a digital transmission system. A sample timer provides a sample pulse at the beginning of each sample interval and a sample clock pulse during the sample pulse. The sample interval includes a plurality of frames and the sample pulse occurs intermediate of the framing pattern. A logic arrangement is responsive to the error output pulse, the sample clock pulse and the sample pulse for providing an alarm indication when the number of error pulses equals or exceeds a first predetermined number during a sample interval. Conversely, the logic arrangement eliminates the alarm indication if the number of errors in a subsequent sample interval is less than a second predetermined number.

Abstract: A narrow-band RC active bandpass filter, in which the center frequency may be changed by changing the resistance values of certain resistive elements, has the certain resistive elements switchably connectable into and out of the RC network so that the ratio of time during which the resistors are connected to the network to the time during which resistors are not connected to the network determines the effective resistance thereof. A programmable timing circuit has a plurality of outputs with each output supplying a different number of equal width pulses during a predetermined like time period whereby each output corresponds to a different ratio. The timing circuit actuates and deactuates the switchable connection from a selected output thus deriving the required effective resistance for a predetermined center frequency.

Abstract: A self-checking pulse density analyzer includes substantially similar first and second threshold detection circuits, each of which have one input connected to receive incoming pulse information to be analyzed, and each of which provide the same binary signal state at a separate output terminal, when the pulse density reaches a predetermined level. Each output terminal is connected to a separate input terminal of a threshold equalizing circuit and to respective inputs of first and second gating circuits. The threshold equalizing circuit is activated by the binary signal from the faster acting threshold detection circuit to speed up the operation of the slower threshold detection circuit and, thus, minimize the difference in operating time betwee the two circuits. These two nearly simultaneous binary indications cause the first gating circuit to operate and, thus, provide a particular binary output signal indicative thereof.