Abstract: A frame search control circuit for a digital transmission system includes an eight bit preview store and a four stage counter. At the beginning of each frame a timing device causes the eight stored bits to be sequentially read out into a comparator for a comparison with bits from the incoming bit stream. The incoming bits are stored in the preview store simultaneously with the read out to the comparator. For an in-frame condition only the first comparison is important and the remaining comparisons are ignored. Further, a count of eight is loaded into the four stage counter which limits the count to eight allowing only eight bits from the incoming bit stream to be read into the preview store, the framing bit being read in first so as to be available for comparison at the next framing interval. For an out-of-frame condition, the timing device initiates the sequential comparison beginning with the framing interval and in this case, each comparison is important.

Abstract: A first network can be switched into and out of connection with a lowpass filter disposed at one of the two opposite carrier terminal ends of a loop transmission path employing a double-sideband carrier. When the filter and network are so connected, an oscillator producing a first test signal of selected frequency and amplitude is formed. This signal modulates the carrier wave generated by the existing carrier oscillator at this terminal end. The modulated signal passes along the path to the opposite terminal end where it is demodulated and detected. The detector threshold is set so that the detector responds to the demodulated first test signal, but does not respond to normal voice and other test signals. The detected demodulated signal energizes the station carrier oscillator at the opposite end whereby its carrier wave is modulated. The resultant second modulated test signal passes back along the path to the original terminal where it is demodulated, and the presence of the carrier is detected.

Abstract: A weighted resistance network under control of combinational and sequential logic circuits provides a separate reference voltage at each of the digit times of the pulse code for comparison with an amplitude sample at the coder input. The difference voltage is used to derive the pulse code which is compressed in a piece-wise manner because of the use of a weighted resistance network. A decoder operates in a similar manner to produce a quantized output from a weighted network under control of a logic circuit responsive to the incoming uniform pulse code.

Abstract: A double sideband suppressed carrier (DSBSC) modulator for operation from unbalanced carrier frequency and modulation frequency sources has the input terminals of first and second constant current amplifiers connected to receive the modulation frequency output signal from the unbalanced source. The first and second constant current amplifiers provide in-phase and out-of-phase modulation frequency signals at respective high impedance output terminals for connection to a modulator. The modulator comprises a quad, i.e., four transistors connected to provide a pair of differential amplifiers. Transistors 1 and 2 comprising the first of the pair and transistors 3 and 4 comprising the second of the differential pair. The emitters of each differential amplifier are tied together.

Abstract: A calibrated unipolar signal is used to deviate a frequency modulator by a predetermined amount .DELTA.f from a carrier f.sub.2. An automatic frequency control circuit operates to bring the carrier back on frequency and a meter connected in the control circuit will read this departure from normal. During the test for correct deviation, a frequency shifter compensates for the predetermined frequency deviation and the meter would so indicate, e.g., would not change reading from that of carrier alone, if the deviation caused by the calibrated unipolar signal is equal to that incorporated in the frequency shifter. If the reading does change, the modulation sensitivity of the frequency modulator is adjusted until the readings before test (using carrier only) are the same as those under test.

Abstract: A circuit for obtaining clock timing information from an equalized pseudo-ternary signal, such as is exemplified by a signal using the modified duobinary code, includes a level selector in which the signal is sliced at a predetermined amplitude. A slicing level reference circuit provides the threshold voltage for the level selector so that only the upper level portion of the original is obtained for processing. This upper level portion is applied to an amplifier and then to a frequency selection circuit which is tuned to the clock frequency of the original signal.

Abstract: Single errors can be detected and corrected in a signal employing a 3-level modified duobinary code. Error correction is predicated on the concept of maximum likelihood of error for the bit having the maximum departure from normal amplitude (error differential). A converter accepts the modified duobinary signal, decodes the signal to obtain a binary output signal and determines the error differential for each bit. Bits of the binary output signals are temporarily stored in a sequential storage device. The error differential is applied to an input of an error analyzer. An error detector determines if an error has occurred during an error correction interval which interval is established by successive extreme levels of the modified duobinary signal. The error analyzer tracks the location of the bit having the largest error differential during each error correction interval.

Abstract: A buffer amplifier, which prevents loading of the input signal, accepts at its input an amplified and equalized pseudo-ternary signal. The output of the buffer amplifier is a-c coupled to the input of a precision differential amplifier, from which two output signals are obtained. One said output signal is representative of the positive pulses and the other said output signal is representative of the negative pulses of the pseudo-ternary signal. These two output signals are both applied to the inputs of a peak detector and a slicer. The d-c output of the peak detector is also applied as one input to the slicer. Separate outputs are obtained from the slicer, one each for the positive and negative pulse inputs, and these two outputs are summed, and the summed output is then amplified to provide a clock driver output.

Abstract: This chassis has side, top, bottom and rear plates which are made out of sheet stock and where are oriented at 90.degree. with respect to each other. Bifurcated tongues are formed in edges of plates. Elongated slots are also formed in plates at points spaced away from the edges thereof. The slots and tongues are dimensioned and oriented on the plates such that in an assembled shelf, the bifurcated tongues are located in associated slots so as to form square openings defined by walls of the associated slots and bifurcations-openings. Self-tapping screws threaded into the square openings and axially aligned bifurcations-openings cut threads in the walls defining these aligned openings over the full grip length of the screws to hold the plates together.

Abstract: Modified duobinary regenerative repeaters are tested in situ by means of a pulse pattern generator connected to the repeatered span line, a plurality of audio filters, one at each repeater site, a return transmission path and a measuring device for determining the character of the signal output from a selected repeater.

Abstract: The correlation properties of a 7-level correlative waveform permit detection of errors due to irregularities and impairments in the transmission facility, where these errors violate the correlation patterns of the waveform. The received 7-level correlative waveform is first decoded to obtain a pair of binary outputs which are representative of the original binary signal at the transmitter, except for errors that might have occurred during the transmission period. The pair of binary signals are operated on to obtain coded binary signals and their delayed counterparts. These coded binary signals are used to establish the effect of presence or absence of a top or bottom level that would result from the formation of a nonbinary correlative signal. If an error has occurred during transmission, the extreme levels of the locally generated signal will not normally coincide with those of the received signal.

Abstract: The embedding network of a microwave oscillator comprises three lengths of parallel conductors supported above a ground plane and having odd and even mode short circuits thereon. Two of the conductors are connected to different ones of the electrodes of a bipolar microwave transistor which has a third electrode connected to ground. A load is connected between the third conductor and ground. Physical and electrical characteristics of the network are varied to cause parameters thereof to be desired values which yield maximum output power and oscillation at desired frequencies.

Abstract: A substrate carrying electrical circuit patterns and elements is supported in an upright position on a printed circuit board by a clip so as to restrict rotational movement of the substrate from that position when pins and plated through holes on the substrate and board are engaged. The clip comprises a body having a flat bottom for contacting one side of the board and a first-cylindrical peg depending from the bottom. Spaced-apart sections on one side of the body are in a common plane perpendicular to the bottom with a protrusion near the top of the body extending beyond this plane. A second-rectangular peg also extends from the one side of the body past the common plane, with the base of the second peg being in line with the flat bottom. A trough in the protrusion receives one edge of the substrate, with one side of the latter contacting the side sections in the common plane, and the opposing edge of the substrate being proximate the bottom of the body.

Abstract: Apparatus and method for generating a multilevel correlative signal wherein the multiple levels are digitally generated. A serial binary bit stream is first converted into two parallel binary bit streams each at half the bit rate of the original serial binary bit stream. The parallel bit streams are encoded in accordance with the relation B = C - .DELTA..sup.2 C MOD 4; where B is the original waveform, C is the resultant waveform, and .DELTA..sup.2 indicates two units delay or 2T seconds where 1/T is the parallel speed in digits per second. Next the binary encoded bit streams are digitally converted to a 7-level waveform; and, finally the 7-level waveform is transformed into an analog signal which retains the 7-levels and provides a band limited 7-level signal related on a one-to-one basis to the binary input signal.

Abstract: A modified duobinary signal is separated into two (odd and even) pulse trains, each of which is representative of a bipolar pulse train. Each representative bipolar pulse train has a bit rate one-half that of the modified duobinary signal. Violations of the modified duobinary coding rules appear as violation of the bipolar coding rules. The bipolar violations which occur are detected separately for the odd and even pulse trains. The detected errors are read into an error combiner and are read out serially at the original modified duobinary bit rate.

Abstract: An initial error indicated by a pulse at the binary input is applied through a gating circuit to trigger a monostable multivibrator (one-shot) to start a timing interval. The output of the one-shot is applied to a second gating circuit which inhibits the first gating circuit to prevent retriggering of the one-shot. Subsequent error pulses are then applied directly to a counting mechanism which counts the errors which occur during the predetermined time interval established by the one-shot. An acceptable error density is established by the predetermined time interval for the one-shot in relation to the number of errors that would occur during this predetermined time interval. If the number of errors which occur exceeds the acceptable error density, the counting circuit puts out a signal which may be applied to an alarm (or framing) circuit. Once the error counter produces an output, i.e.

Abstract: An end-office repeater accepts a high-speed bipolar signal, converts the bipolar signal into a unipolar signal, scrambles the unipolar signal, and encodes the scrambled unipolar signal into a modified duobinary signal for transmission over a cable pair. Before cable loss would severely degrade the duobinary signal, line repeaters and/or inter-office repeaters are installed at predetermined intervals so as to equalize and regenerate the modified duobinary signal. By so doing, the signal is recovered with acceptable phase jitter, which permits recovery of the original high-speed bipolar signal at the distant end of a repeatered span line. The receiving-end office repeater equalizes and regenerates the modified duobinary signal, decodes the signal to obtain a unipolar signal, descrambles the unipolar signal, and converts the unipolar signal into a bipolar signal.Detection of errors in the modified duobinary signal may be obtained without adding redundant digits.

Abstract: In PCM transmission, it is well known to transmit 24 voice-grade channels at a bit rate of 1.544 Megabits per second (Mb/s). The number of channels which may be transmitted in about the same bandwidth is doubled by the use of correlative level coding, such as the modified duobinary technique. Because of the degradation experienced by the modified duobinary signal in passing over cable pairs, periodic regeneration of the signals is required for effective transmission. The present invention is directed to a regenerative repeater which equalizes, amplifies, reshapes, and retimes the received modified duobinary signal so as to provide a regenerated signal which is nearly identical with that originally transmitted.

Abstract: Printed circuit boards are moved in a conveyor with the underside of flat boards spaced a prescribed distance above the top surface of a rotating cutting disk. In order to protect the circuit patterns on the underside of the board and the board itself, a V-shaped wheel is loosely rotatably supported on a shaft with the wheel being in front of and orthogonal to the cutting disk. The height of the wheel is adjusted such that the uppermost point on the circumference thereof is in the line of travel of the boards. Movement of a board that is bowed downward in the direction of the disk causes the wheel to roll on the underside of the board and to raise the board above the top of the cutting disk. In this manner, the underside of warped circuit boards is maintained at least a prescribed distance above the top surface of the cutting disk as the board moves over the leading - cutting edge of the latter and component leads are trimmed thereby.

Abstract: The dies here comprise opposed sets of parallel-elongated members which are arranged for engagement to form component leads. Members at opposite ends of the dies cooperate in pairs to cut axial leads of a component positioned between the dies to prescribed lengths when the dies are engaged. A third member of one die has a slot through one of a pair of opposite sides thereof that are adjacent one end thereof and the component. A second pair of elongated members of the other die are positioned to move adjacent the opposite sides of the third member. When one lead of a component is held against the one end of the third member, with one ends of the second pair of members being proximate the component body and the free end of the one lead, engagement of the dies causes the second pair of members to force a portion of the component body into the slot and the one lead adjacent to the other opposite side of the third member to form the component leads into a hairpin pattern.