Abstract: This protector holder includes a plurality of double ended spring terminals which are arranged in a row in a housing that is made up of mating body halves. Each spring terminal includes a folded ribbon contact and adjacent-facing folded finger contacts formed on opposite ends thereof which are connected together by a shank. Each body half has a plurality of openings arranged in a row in one side thereof, each opening having a slot extending through the top wall and one side of the body half and having a trough in the one side of the latter body half which extends through the bottom wall thereof. The finger contacts and shanks of spring terminals are located in associated openings and slots, respectively, with the folded ribbon contacts extending above the top wall of a body half in pairs which face each other. A pair of body halves mate such that the slots and openings form slotted compartments in a housing which hold the shanks and finger contacts of the terminals in place.

Abstract: The frequency of a microwave oscillator is stabilized by coupling a portion of the RF signal therefrom to an HF oscillator operating at a sub-multiple of the microwave frequency and producing a strong harmonic at the microwave frequency in order to cause the operation of the microwave and HF oscillators to be locked together. The HF signal frequency, which includes any drift in the microwave oscillator frequency, is divided down a specified amount and compared with the frequency of a stable crystal reference oscillator in a comparator. The output of the comparator is a DC error voltage which is proportional to any drift in the frequency of the microwave oscillator. This error voltage is applied to the microwave oscillator to cause the operating frequency thereof to be more nearly constant.

Abstract: In this converter, a common transistor Q2 is one of the two transistors Q1 and Q2 of a multivibrator and is also one of a pair of power switching transistors Q2 and Q3 that are connected in series across an input port receiving an input voltage-V of one polarity. The other transistor Q1 of the multivibrator is also connected across the input port. The multivibrator causes the switching transistors Q2 and Q3 to be alternately conducting and nonconducting. A pair of capacitors C3 and C4 and unidirectional diodes D4, D5, and D6 are connected to the switching transistors Q2 and Q3 in such a manner that only one capacitor C3 is charged in one direction during conduction of the common transistor Q2, and that this one capacitor C3 discharges through the other capacitor C4 to charge the latter and produce an output voltage of the other polarity across it and an output port only during conduction of the other switching transistor Q3.

Abstract: A Bode equalizer which has as one active element thereof a high-gain, differential-input amplifier and which has as a second active element a variable negative resistance, the equalizer circuit being controlled by a resistance arrangement which effectively comprises a series-connected, fixed resistor and the variable negative resistance.

Abstract: First, second, and third single-input, single-output operational amplifiers having associated input resistors and feedback resistors are connected in series between input and output terminals. First and second capacitors are also connected across associated first and second amplifiers to provide a second-order network transfer function. A fourth feedback resistor is connected between the output terminal of the third amplifier and the amplifier side of the first input resistor. The amplifier input sides of the second and third input resistors are also connected through associated feed-forward resistors to the one side of the first input resistor that is spaced from the first amplifier. Appropriate selection of element values enables synthesis of circuits having prescribed biquadratic transfer functions.

Abstract: A data buffer makes use of a plurality of buffer storage cells into which serial bit streams are sequentially written, in order to obtain correction for phase jitter. A write clock signal is derived from the serial bit stream and is used to sequentially write the digits into the cells. A stable clock source is used to provide the basic timing for sequentially reading the bits out from the buffer storage cells, and a logic circuit is used in conjunction therewith to obtain the retimed serial bit stream. The write and read timing signals should have a maximum time separation to allow for maximum correction of phase jitter, and it is critical that the write and read signals should alternate. A monitor and reset circuit compares a selected write signal with a selected read signal and, where a violation of the alternating write-read condition occurs, the circuit resets the write timing and holds it until the read timing has attained a particular state.

Abstract: A decoded PAM input signal is coupled through a first polarity switch (which for one polarity of a polarity signal is closed) to the positive input line of a differential operational amplifier and through the series combination of a second polarity switch (which is open for the one polarity) and an input resistor to the negative input line of the differential amplifier. The positive input line is resistively connected to ground through a first bias resistor and is also connected to ground through the series combination of a second bias resistor and a third polarity switch which is also open for the one polarity. A feedback resistor is connected between the output line and the negative input line of the amplifier.

Abstract: Gain control circuits in the base and emitter circuits of a common-emitter transistor amplifier stage each include pluralities of resistors and electrically conductive screw-type switches which are connected together such that the net changes in decibel values of gain provided by closing individual switches are cumulative. Resistors in the emitter gain control circuit are electrically connected in parallel with the emitter resistor in the AC equivalent of the amplifier in various configurations by closing screw switches to decrease the effective emitter resistance and thereby increase the decibel value of amplifier gain in steps of prescribed magnitudes. The switches are selectively closed in a prescribed manner to provide step changes in the decibel value of the net gain of the stage in discrete consecutive steps of the same magnitude. Transistor amplifiers with emitter gain control circuits may be connected in series to provide additional steps and range of voltage gain.

Abstract: A negative, edge-triggered R-S latch, which provides predetermined output states for any and all R-S inputs, may be obtained by using an AND-OR-Invert (A-O-I) circuit in conjunction with a "D"-type flip-flop. The reset input and the Q-output of the flip-flop provide the inputs to one AND-gate of the A-O-I circuit. The set input and Q-output of the flip-flop provide the inputs to the other AND-gate. The output of the A-O-I provides the clock input to the flip-flop. The Q-output is also connected to the D-input of the flip-flop.

Abstract: A novel nonfrequency-converting microwave radio repeater for use in multichannel telecommunications is disclosed. A single microwave amplifier provides the requisite gain for two different angle-modulated radio frequency signals. Bandpass filters and circulators permit duplex operation by channeling the received signals through the repeater. The two radio frequency signals are amplified simultaneously in the same amplifier and then separated to be retransmitted at the same frequency in the proper path direction.

Abstract: A threaded invar tuning screw extending through the threaded aperture of an invar bushing in the broad wall of a waveguide filter presents a capacitance inside the waveguide. This capacitance is varied by changing the depth of the screw in the waveguide in order to tune the filter. A brass locknut on the screw has a truncated, conically shaped bottom that mates with a similarly shaped countersunk hole on the bushing, the conical bottom, countersunk hole, and screw being coaxial. The mating surfaces on the nut and the countersunk hole reduce lateral movement of the screw during tuning and fixing of the position of the latter by tightening the locknut against the bushing.

Abstract: An analog-to-digital converter employing a sample-hold, ramp generator and comparator in the conversion process combines the sample-hold and integrate functions in one operational amplifier. Provision may be made to derive the reference voltage, for the ramp generator, from the analog signal whereby automatic gain control is also obtained.

Abstract: The square-wave output of a comparator is coupled back to the input of an RC controlled integrator including an operational amplifier and an inverter circuit with an output signal maintained at a predetermined level. The RC network sets the pulse repetition rate of the square wave. The inverter and integrator outputs are connected to separate inputs of the comparator. A gating circuit couples a data source to the operational amplifier. In particular, the gating circuit couples an additional square-wave current to the integrator via a resistor. The square-wave current may be in phase and raise the pulse repetition rate of the resulting square wave or out of phase and lower the pulse repetition rate.

Abstract: Support members are located near the corners of a pair of printed circuit cards for holding them together in a fixed, spaced-apart, adjacent and parallel relationship. Each card has a group of holes formed in the same pattern in each of the four corners thereof, at least one hole of each group extending all the way through the card. Each support member comprises a pair of plates that are joined together at a 90.degree. angle along one edges thereof. Load-bearing pegs project from parallel, non-joined together edges of one plate. Flexible posts project from parallel, non-joined together edges of the other plate. An arm extends from each post proximate the end thereof that is spaced from the other plate and in a direction substantially parallel to said parallel edges of the other plate.

Abstract: In a system employing half-span preemphasis of transmitted signals on a cable pair telephone line, equalization is accomplished in a circuit arrangement including first and second complementary constant-resistance networks having the input impedances thereof in the emitter and collector circuits, respectively, of a common emitter amplifier. These impedances control the feedback and gain of the amplifier such that their effects are additive in a particular manner in the collector-output circuit thereof. The terminating resistances of the networks are the resistances produced by a pair of differentially controlled thermistors. A DC error signal that is proportional to line length controls the current driving the thermistors and thus the resistances thereof. When the circuit arrangement is at half-span spacing, a difference circuit causes the terminating resistances of the thermistors to be the same values, which make the impedance characteristics of the networks such that the net gain of the amplifier is flat.

Abstract: A composite test signal consisting of a search test signal and a sweep test signal from a link test set is combined with the through-path traffic signals during in-service testing. The composite signals are simultaneously applied to a transmitter of a microwave radio communication link under test. The sweep signal level is adjusted at the microwave radio communication link transmitter so that the total FM deviation is limited to the normal IF or RF transmission frequency band. The composite test signals and traffic signals are received and split into a through path signal and a test path signal. In the through path, the test signals are blocked, and the traffic signals are transmitted to the next microwave radio hop. In the test path, the traffic signals are blocked, and the test signals are applied to the receive section of a link test set. The link test set is then used to measure the transmission characteristics of the microwave radio communication link under test.

Abstract: In a digital communication system, apparatus for upconverting the bit rate, f.sub.1, of a digital data source to permit digital transmission at a bit rate f.sub.2, where f.sub.2 > f.sub.1. Pulse stuffing techniques are used to insert a fixed number of time slots in the digital data signal such that the ratio of information time slots to stuffed time slots remains constant. The upconverted signal, consisting of nonredundant data bits and stuffed time slots, is interleaved with framing bits prior to transmission over a digital facility. The framing bits provide the synchronization information to enable the receiver to identify the added time slots and to selectively remove the information data bits from the transmitted line signal. The desired data bits are then restored to their original f.sub.1 bit rate.

Abstract: Matched voltage-controlled resistances are provided across the drain-to-source channels of a pair of FET's, each FET having a gate electrode connected through an associated control resistor to the same one terminal of a source of DC control voltage; having a source electrode electrically connected to the same other terminal of the voltage source; and having an associated feedback resistor electrically connected between its drain and gate electrodes. The drain electrodes are preferably capacitively coupled to input or output terminals to prevent DC loading of the FET network by external circuitry. A resistor is also connected across the drain-to-source channel of each FET to limit the maximum value of net resistance presented thereby. The resistance of one of the control resistors is adjusted to have a value which causes the net drain-to-source resistance of the associated FET to have the same value as that of the other FET for a particular value of control voltage.

Abstract: In this test set, each one of a pair of resistive bridges has one node thereof connected to ground, one of the arms of each bridge that is adjacent the one nodes being open. Each one of a pair of ungrounded terminals of a balanced circuit under test is connected to a different one of the ungrounded nodes associated with the open arms of the bridges. Any center ground terminal of the test circuit is connected to the one nodes, which are grounded. Equal amplitude test signals of the same phase are applied to the pair of nodes on the two bridges that are adjacent to the one nodes thereof. A reflected signal coupled from the pair of nodes on the two bridges that are opposite the one nodes thereof is applied to a VTVM which provides an indication of the return loss of the test set, in relation to the individual bridge resistances which are the same values.

Abstract: Gain control circuits associated with the base and emitter electrodes of a common-emitter transistor amplifier stage include pluralities of electrically conductive screw-type switches and resistors. The net gains provided by the associated gain control circuits are cumulative and determine the net gain of the stage. The gain changes provided by individual switches of the base and emitter gain control circuits are also cumulative, the switches being selectively closed in a prescribed manner to provide step changes in the decibel value of the net gain of the stage in discrete steps of the same magnitude. A plurality of transistor amplifiers with associated emitter gain control circuits may be connected in series, with the decibel values of voltage gains thereof also being additive, to provide additional steps and range of voltage gain. Series resistors in the base gain control circuit are selectively short-circuited by screw switches to decrease the input resistance of the amplifier stage.