Patents Represented by Attorney, Agent or Law Firm Lester H. Birnbaum
  • Solder assembly of components
    Patent number: 5014162
    Abstract: Disclosed is an apparatus involving soldering of components, such as the soldering of flexible circuits to printed circuit boards. Holes are provided in the areas of one component which are to be soldered to pads on the other component. Precise amounts of solder are provided to each pad, preferably by a shuttle element which carries solder paste in cavities corresponding to the pads and which deposits the solder on the pads when the solder is melted. The holes in the component are aligned with the pads, and the solder is reflowed so that a visible solder fillet is formed above the holes to permit inspection of the solder joint.
    Type: Grant
    Filed: June 27, 1989
    Date of Patent: May 7, 1991
    Assignee: AT&T Bell Laboratories
    Inventors: William A. Clark, Michael A. Oien, Walter Pelosi
  • Vapor processing of a substrate
    Patent number: 4980314
    Abstract: Proposed is a method of fabricating semiconductor devices involving vapor etching of channels and/or growth of layers in a substrate. The etch or growth rate is controlled by opening up additional regions in the mask which are separated from the opening used to define the active region. The etching or growth in the additional exposed regions of the substrate consumes a certain amount of reactant and controllably reduces the amount available for etching or growth in the active region.
    Type: Grant
    Filed: June 6, 1989
    Date of Patent: December 25, 1990
    Assignee: AT&T Bell Laboratories
    Inventor: Keith E. Strege
  • Electroless silver coating for dielectric filter
    Patent number: 4965094
    Abstract: Disclosed is a method for forming silver coatings on material, particularly ceramic filter material. The surface is first sensitized by applying thereto a solution comprising a silver ammonia complex and a solution comprising a reducing agent. This forms a thin silver coating which is then silver plated.
    Type: Grant
    Filed: December 27, 1988
    Date of Patent: October 23, 1990
    Assignee: AT&T Bell Laboratories
    Inventor: Harold E. Fuchs
  • Interconnection medium
    Patent number: 4959555
    Abstract: Proposed is an interconnection medium which is tolerant of faults in at least one of the conductors. Redundancy is established to components connected to the medium by providing additional conductors and steering the signals between components to appropriate conductors in the event of a fault. Preferably, the conductors are arranged in a way which balances the amount of additional wiring and the amount of added parasitic loading.
    Type: Grant
    Filed: April 27, 1989
    Date of Patent: September 25, 1990
    Assignee: AT&T Bell Laboratories
    Inventor: Douglas C. Schmidt
  • Continuous plating method and apparatus
    Patent number: 4959129
    Abstract: Disclosed is a method and apparatus for plating metal onto wire or ribbon. The wire or ribbon is wrapped around two or more barrels with grooves formed around the outside surface. The barrel is immersed within an appropriate electroless or electroplating solution, and rotated at a speed depending upon the immersion time needed for a particular desired plated thickness.
    Type: Grant
    Filed: May 23, 1989
    Date of Patent: September 25, 1990
    Assignee: AT&T Bell Laboratories
    Inventors: Harold E. Fuchs, Robert E. McAnany
  • Identification of workpiece information
    Patent number: 4947335
    Abstract: Disclosed is a method and apparatus for identifying the lot codes of workpieces, such as printed circuit board panels, as they progress down a manufacturing line. At an initial stage of processing, a hole pattern is drilled along one edge of the pieces. The hole pattern includes the lot code number of that piece in binary form. The hole pattern can be addressed by appropriate optical means such as an LED-phototransistor combination or by a video camera as the pieces pass by in order to determine the lot code or other information at any desired point in the processing.
    Type: Grant
    Filed: September 12, 1988
    Date of Patent: August 7, 1990
    Assignee: AT&T Bell Laboratories
    Inventor: Frank H. Blitchington
  • CMOS to ECL output buffer circuit
    Patent number: 4947061
    Abstract: Disclosed is an output buffer circuit which converts from CMOS to ECL voltage levels using only CMOS technology. An external resistor provides the buffer with reference voltage levels in combination with a reference circuit. The high and low voltage references are coupled to the gates of separate biasing transistors in separate branches of the buffer circuit. A third transistor controls whether one or both branches will be coupled to the buffer output. In the first case, the low voltage level is established, and in the second case, the high voltage level is set. Additional transistors can be provided to remove charge buildup on the third transistor.
    Type: Grant
    Filed: February 13, 1989
    Date of Patent: August 7, 1990
    Assignee: AT&T Bell Laboratories
    Inventors: Peter C. Metz, Robert L. Pritchett
  • Optical fiber connector including serpentine grooved member actuated by longitudinal forces
    Patent number: 4867523
    Abstract: Disclosed is an optical fiber connector useful for high density arrays. A rotating mechanism is employed around the fiber ferrule in combination with a spring so as to engage one or more tabs on the connector sleeve. The rotating mechanism includes a serpentine type groove configuration which captures the tabs when the ferrule is pushed into the sleeve and releases the tabs when a longitudinal force is again applied to the ferrule.
    Type: Grant
    Filed: October 28, 1988
    Date of Patent: September 19, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventor: Charles W. Scott, Jr.
  • Fabrication of leaded packages
    Patent number: 4841630
    Abstract: Disclosed is a method of fabricating leaded packages, including protection of the leads during various processing steps. The packages are mounted in special carriers such that the leads are shielded from loads which might otherwise cause damage to the leads.
    Type: Grant
    Filed: March 11, 1988
    Date of Patent: June 27, 1989
    Inventors: Leon Lubranski, Theodore J. Sattler
  • Gas plasma display
    Patent number: 4833463
    Abstract: Disclosed is an ac plasma display of the type employing three electrodes per pel which is useful for full color displays. A phosphor layer is provided over the cover electrodes and the usual electron emission layer is eliminated or thinned down. An additional pulse is provided to the cover electrodes to aid in charge transfer during the write stage in order to compensate for the absence of significant electron emission.
    Type: Grant
    Filed: September 26, 1986
    Date of Patent: May 23, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: George W. Dick, Denis D. Manchon, Jr.
  • Radiation hardened semiconductor devices
    Patent number: 4825278
    Abstract: Disclosed are semiconductor devices and circuits which are highly resistant to the effects of radiation. A thin conductive layer, which is biased at substrate potential, and a thin oxide are provided under the usual field oxide of the devices. The conductive layer shields the semiconductor substrate from the effects of charge generation in the field oxide due to radiation absorption.
    Type: Grant
    Filed: March 2, 1987
    Date of Patent: April 25, 1989
    Assignee: American Telephone and Telegraph Company AT&T Bell Laboratories
    Inventors: Steven J. Hillenius, William T. Lynch, Lalita Manchanda
  • Fabrication of FETs with source and drain contacts aligned with the gate electrode
    Patent number: 4822754
    Abstract: A method of fabricating FETs to reduce parasitics. Contact is made to the source and drain regions through a polycrystalline silicon runner which is aligned with the edge of the gate electrode. This is accomplished by providing a multi-level electrode structure including a gate electrode and depositing the polycrystalline silicon layer over the device. The polycrystalline silicon is rendered selectively removable in the portion overlying the gate electrode. When this portion is removed, the remaining polycrystalline is aligned with the gate.
    Type: Grant
    Filed: June 12, 1984
    Date of Patent: April 18, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: William T. Lynch, Frederick Vratny
  • Fabrication of CPI layers
    Patent number: 4820376
    Abstract: Disclosed is a method of fabricating conductive polymer interconnect (CPI) material which employs chains of electrically conductive particles within an elastomeric matrix. Contact resistance is improved by removing a thin layer is elastomeric material which remains after normal processing. The surface layer is removed by plasma etching so that the conductive particles protrude at both surfaces. The protruding particles can be plated to replace any conductive material removed by the etch.
    Type: Grant
    Filed: November 5, 1987
    Date of Patent: April 11, 1989
    Assignee: American Telephone and Telegraph Company AT&T Bell Laboratories
    Inventors: William R. Lambert, Neng-Hsing Lu, Ray D. Rust
  • Optical connector
    Patent number: 4818058
    Abstract: Disclosed is a connector for optical fibers and components, and a method of manufacture, which provides close alignment. Each fiber is disposed within a plug comprising two blocks placed with their major surfaces in contact. Each block has an array of grooves formed in a major surface for accommodating the fibers. A pair of deeper grooves is also formed in each major surface at opposite edges of each block and at the same time as the array of grooves to form beveled edge surfaces. Guiding rods are disposed against the beveled surfaces so that the rods are rectilinear with the fibers.
    Type: Grant
    Filed: March 3, 1988
    Date of Patent: April 4, 1989
    Assignee: American Telephone and Telegraph Company AT&T Bell Laboratories
    Inventor: Rocco Bonanni
  • Method and apparatus for continuous throughput in a vacuum environment
    Patent number: 4812101
    Abstract: Disclosed is a method and apparatus for continuous introduction and exit of workpieces into and out of a vacuum. A first seal is provided between the atmosphere and a first pumping station. This seal comprises compliant members positioned within cavities in a plate so that the pressure differential causes the members to push against the workpiece and the cavity wall to establish a rotating seal. A second seal may also be provided between the first pumping station and the vacuum chabmer. This seal includes compliant members mounted within a series of differentially pumped cavities and providing a low friction seal with the workpiece.
    Type: Grant
    Filed: April 27, 1987
    Date of Patent: March 14, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Carroll H. George, Guy W. Lynott, Andrew N. Pargellis
  • High frequency connector
    Patent number: 4806107
    Abstract: Disclosed is a high frequency connector employing a plurality of columns of female contacts for receiving signal carriers and ground/power blades providing shielding between the columns of female contacts. The signal and ground/power blades are coupled to a circuit pack by means of a plurality of flexible circuit sheets. The connector provides full shielding of the signal carriers to the backplane.
    Type: Grant
    Filed: October 16, 1987
    Date of Patent: February 21, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Richard M. Arnold, Paul A. Baker, Coleen A. Drucker, Robert J. Gashler, Dominic T. Lipari, Max S. Robin, Howard C. Schell
  • Electronic component package using multi-level lead frames
    Patent number: 4801765
    Abstract: Disclosed is a semiconductor package with a high pin count. External contacts to the chip are provided by interdigitated leads formed from an upper and lower lead frame. The lower lead frame includes a paddle for mounting the chip. The upper lead frame initially has its leads tied together and a center portion is punched out to fit the size of the particular chip. The two lead frames are preferably coplanar in the area around the boundaries of the package encapsulant.
    Type: Grant
    Filed: January 6, 1986
    Date of Patent: January 31, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventors: Harold W. Moyer, Harry R. Scholz
  • Fabrication of mercury switches
    Patent number: 4795659
    Abstract: Disclosed is a method of fabricating mercury switches. The switches are actived by loading a batch into a common housing of a fixture. The fixture is then rotated in a furnace at a slow speed to prevent breakage. The fixture may include a mesh cage housing to allow rapid heating and cooling.
    Type: Grant
    Filed: August 3, 1987
    Date of Patent: January 3, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Bell Laboratories
    Inventor: Timothy M. Kellis
  • Multilayer circuit board fabrication process
    Patent number: 4795693
    Abstract: Printed circuit boards having a plurality of circuit layers are produced on a copper-clad substrate by first forming a pattern in a desired configuration to produce the first layer of the printed circuit board, then covering it with an energy-sensitive material comprising a rubber modified epoxy resin, an acrylated epoxy resin and a viscosity modifier; the energy-sensitive material is delineated in a desired pattern and developed to uncover portions of the underlying metallization pattern and the entire substrate is then blanket cured to produce a rigid layer having openings in appropriate places; the openings are metallized and a second copper pattern is produced on the cured polymer by conventional metallization and lithographic techniques. If desired, the process is repeated until a suitable number of copper patterned levels are obtained.
    Type: Grant
    Filed: November 21, 1986
    Date of Patent: January 3, 1989
    Assignee: American Telephone and Telegraph Company, AT&T Technologies, Inc.
    Inventors: Jose A. Ors, Richard D. Small, Jr.
  • Semiconductor package with high density I/O lead connection
    Patent number: 4774635
    Abstract: Disclosed is a semiconductor package which permits coupling of semiconductor bond pads to I/O leads where a high density of connections is needed. Conductive fingers backed by an insulating tape are bonded to the ends of the fingers on a lead frame. The tape fingers are electrically coupled to the bond pads on one major surface of the semiconductor chip by wire bonding. In one embodiment, the opposite major surface of the chip is bonded to a paddle on the lead frame through an aperture in the tape for maximum heat dissipation.
    Type: Grant
    Filed: May 27, 1986
    Date of Patent: September 27, 1988
    Assignee: American Telephone and Telegraph Company AT&T Bell Laboratories
    Inventors: Lawrence A. Greenberg, David J. Lando