Patents Represented by Attorney, Agent or Law Firm Limbach & Limbach LLP
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Patent number: 6148043Abstract: In a branch metric calculating circuit, using a sample value `y` input from an A/D converter and reference levels {-1, -1/2, 1/2, 1}, branch metric calculation is performed by squaring a difference between the sample value `y` and each of the reference levels and subtracting the square of the sample value `y` from the resultant value of squaring the difference. Since actual calculation is carried out for values 2y, y-3/4, -y-3/4 and -2y in this arrangement, square operation circuits can be eliminated, thereby making it possible to simplify a configuration of a Viterbi decoder.Type: GrantFiled: November 18, 1997Date of Patent: November 14, 2000Assignee: Sony CorporationInventor: Kensuke Fujimoto
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Patent number: 6146958Abstract: Disclosed are methods of making inductors and capacitors, comprising filling a via in a dielectric disposed between two metal layers with a metal plug. The plug comprises tungsten, aluminum or copper and extends the length of the metal layers. The plug connects the two metal layers to form the inductor. Two plugs can be formed so as to connect the two metal layers so as to form a parallel plate capacitor.Type: GrantFiled: September 22, 1998Date of Patent: November 14, 2000Assignee: National Semiconductor CorporationInventors: Ji Zhao, Chih Sieh Teng
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Patent number: 6144969Abstract: File name conversion method, and apparatus, for converting a first file name that can be distinguished by a given operating system into a second file name that can be distinguished both by the given operating system and other operating systems. The method and apparatus insure that the first and second file names do not already exist on an associated recording medium prior to recording the first file name on the recording medium and prior to converting the first file name to the second file name. Also provided is a recording medium on which is recorded a file conversion program for converting the first file name to the second file name and for searching whether or not the file names exist on the recording medium.Type: GrantFiled: January 8, 1998Date of Patent: November 7, 2000Assignee: Sony CorporationInventors: Tatsuya Inokuchi, Osamu Udagawa, Yasuyoshi Kaneko, Kazuhisa Taira
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Patent number: 6144629Abstract: A loading device for loading a disc cartridge having a groove formed on its one lateral surface for extending along an inserting direction and a shutter provided for movement along the lateral surface formed with said groove. The loading device includes a holder for insertion of the disc cartridge and for holding the inserted disc cartridge. The holder is movable between a first position for insertion or ejection of the disc cartridge and a second position lowered from the first position. The loading device also includes an ejection lever movably mounted on the holder. The ejection lever is at least partially inserted into the groove of the disc cartridge on completion of insertion of the disc cartridge into the holder, and is biased in a direction of ejecting the disc cartridge inserted into the holder from the holder.Type: GrantFiled: May 4, 1998Date of Patent: November 7, 2000Assignee: Sony CorporationInventors: Kazuhito Kurita, Kiyoshi Toda
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Patent number: 6145045Abstract: An apparatus for an method of sending and receiving data on a Universal Serial Bus using a memory shared among a number of endpoints are disclosed. The memory is a double buffer which allows the next packet to be prepared while the current packet is being transmitted. The invention also supports transmission retry.Type: GrantFiled: January 7, 1998Date of Patent: November 7, 2000Assignee: National Semiconductor CorporationInventors: Ohad Falik, David Brief
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Patent number: 6143641Abstract: In accordance with one embodiment of the invention, a diffusion barrier layer is formed in a copper interconnect structure by first forming a layer of intermetal dielectric material on an underlying layer of conductive material. A pattern of dual damascene structures is then formed in the interconnect dielectric layer. An adhesion layer is then formed on exposed sidewalls of the damascene structure and on the upper surface of the intermetal dielectric material. The adhesion-layer-lined dual damascene structures are then filled with a conductive material that includes copper. The copper-including conductive material is then planarized to the upper surface of the intermetal dielectric material. Intermetal dielectric material is then removed to expose the conductive material. A diffusion barrier material is then deposited on exposed surfaces of the conductive material.Type: GrantFiled: January 26, 2000Date of Patent: November 7, 2000Assignee: National Semiconductor CorporationInventor: Vassili Kitch
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Patent number: 6141489Abstract: A data recording device that can easily and reliably manage a plurality of recording media or information recording surfaces even when a data compression rate largely varies with the contents of the data and that can record, for example, mass image data by effectively preventing the picture quality of an image represented by the image data from being degraded. The data recording device records image data after securing a region according to the preliminarily estimated number of recording media or information recording surfaces at the time of recording image data by using a coding method, by which a data compression rate largely varies with the contents of data. Thereafter, the data recording device records management date used for managing the plurality of recording media or information recording surfaces, on which the coded data is recorded, on the management region according to a result of recording.Type: GrantFiled: May 14, 1996Date of Patent: October 31, 2000Assignee: Sony CorporationInventor: Kazuyuki Honda
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Patent number: 6141624Abstract: A fluid sample contains a plurality of different types of particles of interest. The method sets a limit for the maximum volume of the fluid sample to be analyzed, a limit for each of the different plurality of particle types, and a limit for the maximum number of particles to be analyzed with the maximum number being less than the sum of the limits for each of the different types. In the method, an aliquot of the fluid sample including the particles therein are analyzed to determine the type of the particles. The total volume of aliquots analyzed is counted. The method is stopped in the event the total of aliquots counted equals or exceeds the limit for the maximum value. For each type of particle in the fluid sample determined, a test is made if the total number of particles determined equals or exceeds the limit for each particle type. If the number does not exceed the individual type, the number of particles for that type is added and is counted. The total number of particles for all the types is counted.Type: GrantFiled: May 13, 1997Date of Patent: October 31, 2000Assignee: International Remote Imaging SystemsInventors: Harvey Lee Kasdan, Sanford Widran
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Patent number: 6141251Abstract: In a non-volatile memory array where the memory cells in a sector are programmed together and a plurality of sectors form a segment which are erased together, through the use of a free list linking entries in a register with each entry in a register corresponding to a free segment, a free list table is created which readily simplifies searches for segments that are available for erasure. In addition, through the creation of a segment number table and a count index, determination of particular valid sectors in particular segments can be readily identified.Type: GrantFiled: January 28, 2000Date of Patent: October 31, 2000Assignee: Silicon Storage Technology, Inc.Inventor: Dongsheng Xing
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Patent number: 6141217Abstract: In an enclosed control device including a casing enclosing an electronic circuit in a closed state, a centrifugal fan is also enclosed in the casing for enhancing the cooling of the electronic circuit. With a smoothing capacitor and a semiconductor element heating up, a temperature in the casing increases. Air flows to the side of the centrifugal fan. After passing through the centrifugal fan, the air disperses in the directions along the inner wall of the casing. This flow of air enhances heat transmission from the heated up smoothing capacitor and the semiconductor element to the air, and heat transmission from the air to the casing.Type: GrantFiled: October 1, 1998Date of Patent: October 31, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Takafumi Nakahama, Takayuki Ishii, Tomohiko Tanimoto
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Patent number: 6141711Abstract: A secondary bus controller allows for hot insertion and ejection of devices from the secondary bus without ceasing operations or halting software in the host computer. When a device is to be inserted a signal is sent to the secondary bus controller. The secondary bus controller suspends operation of the secondary bus, placing devices on the secondary bus in stasis. An interrupt handler reconfigures the system for the newly inserted card once it has been inserted. Attempts to access devices on the secondary bus during the insertion process may be met with a retry signal until insertion is complete. The ejection process follows similar steps, isolating and suspending operations on the secondary bus and triggering an interrupt routine in the host processor to reconfigure the system. The host processor and primary busses, along with the secondary bus controller remain active throughout the insertion or ejection processes.Type: GrantFiled: December 19, 1996Date of Patent: October 31, 2000Assignee: National Semiconductor CorporationInventors: Pranay D. Shah, Kenneth C. Ma, Jeffrey A. Hawkey, Kenneth J. Kotlowski
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Patent number: 6139275Abstract: An impeller used for cooling a dynamoelectric machine such as electric motors includes a disk and a plurality of blades arranged on the disk in a circle at unequal spaces so that a position angle .theta.n of an n-th blade is met by an equation:.theta.n=.theta.n0+.theta.max.times.sin {2.pi..times.m.times.(n-1)/Z}where Z is the number of the blades, .theta.n0 is a position angle defining a position of the n-th blade when the blades the number of which is shown by Z are arranged on the disk at equal spaces where 1.ltoreq.n.ltoreq.Z, .theta.max is a maximum allowable angular difference, and m is a degree of a rotational frequency and takes any integer from 1 to Z-1.Type: GrantFiled: July 23, 1999Date of Patent: October 31, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Shinichi Noda, Nobutake Aikura, Takuro Hayashi
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Patent number: 6136705Abstract: A process for the controlled formation of self-aligned dual thickness cobalt silicide layers during the manufacturing of a semiconductor device that requires a minimum number of steps and is compatible with standard MOS processing techniques. In the process according to the present invention, a semiconductor device structure (such as an MOS transistor) is first provided. The semiconductor device structure includes exposed silicon substrate surfaces (such as shallow drain and source regions) and a silicon layer structure disposed above the semiconductor substrate surface (such as a polysilicon gate). A cobalt layer is then deposited over the semiconductor device structure followed by the deposition of a titanium capping layer. Next, the thickness of the titanium capping layer above the silicon layer structure (e.g. a polysilicon gate) is selectively reduced using, for example, chemical mechanical polishing techniques.Type: GrantFiled: October 22, 1998Date of Patent: October 24, 2000Assignee: National Semiconductor CorporationInventor: Christopher S. Blair
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Patent number: 6137946Abstract: A bit stream C is composed in editing work at a high processing speed wherein at least a portion of a bit stream A resulting from MPEG encoding is concatenated with at least a portion of a bit stream B also resulting from MPEG encoding. The amount of data D.sub.A at an end point A.sub.out of a scene A' of the bit stream A and the amount of data D.sub.B at a start point B.sub.in of a scene B' of the bit stream B to be accumulated in a VBV buffer are calculated. The difference between D.sub.A and D.sub.B is used for adjusting the amount of data at a portion of the bit stream C which corresponds to a point of junction between the bit streams A and B. If D.sub.A >D.sub.B, stuffing code is added to a picture at the end point A.sub.out. If D.sub.A <D.sub.B, on the other hand, skipped P pictures are inserted into a location after the picture at the end point A.sub.out.Type: GrantFiled: April 3, 1998Date of Patent: October 24, 2000Assignee: Sony CorporationInventor: Yuji Ando
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Patent number: 6138149Abstract: The electronic mail editing section 26 has a function of editing an electronic mail and inserts a stored index sticker into the text of the electronic mail. The edited electronic mail after insertion of the index sticker is sent to the electronic mail transmitting section 27 by an electronic mail transmitting command, and then transmitted to other information processing apparatus 10b serving as a client computer. The transfer information notifying section 28 sends out transfer information via the internet 7 to the WWW server 8i upon sending the electronic mail by the electronic mail transmitting section 27. The transfer information comprises prescribed information permitting confirmation by the WWW server 8i of the transfer of the information. As a result, the WWW server 8i can know at least that the information processing apparatus 10a has transferred the information to the other information processing apparatus 10b.Type: GrantFiled: June 2, 1998Date of Patent: October 24, 2000Assignee: Sony CorporationInventor: Kazunori Ohmura
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Patent number: 6134149Abstract: A method and an apparatus is provided to decrease the erase current level by subdividing the memory array into small segments and cycle through complete address space sequentially during the chip erase operation. Therefore, the transient erase current is proportionally reduced and is still within the current driving capability of an on-chip pump when a smaller memory segment is chosen. Furthermore, a chip erase operation can be divided into two stages. During the first stage of the chip erase operation, chip erase current is high and is supplied through a V.sub.CC power supply that can deliver a high current, but not a high enough voltage to ensure sufficient erasure of memory cells. During the second stage of the chip erase operation, the erase current is much lower and is supplied through an on-chip charge pump that can deliver much higher voltage than the V.sub.CC power supply to ensure the memory cell array is properly erased.Type: GrantFiled: March 1, 1999Date of Patent: October 17, 2000Assignee: Integrated Memory Technologies, Inc.Inventor: Tien L. Lin
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Patent number: 6134626Abstract: In an information recording method and its device to sequentially write data on a recording medium on a fixed data basis, a command to write the first data formed of the fixed data basis is transmitted from the fixed file system to the writing means of the recording medium, and an actual write result of the first data is returned from the writing means to the file system delaying for the fixed number of commands from the time of transmitting the first data. By inserting link blocks on the data sequence to be recorded on the recording medium and sequentially writing a plurality of packets, the write position shift can be prevented, and by returning an actual write result delaying for the predetermined number of commands, the data writing that is error retrievable using the write cache can be realized.Type: GrantFiled: October 28, 1997Date of Patent: October 17, 2000Assignee: Sony CorporationInventors: Tatsuya Inokuchi, Osamu Udagawa, Shigeki Tsukatani
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Patent number: 6134155Abstract: A FIFO stack is implemented using a DPRAM. One of the ports of the DPRAM is used to add elements to the FIFO stack, and the other port is used to remove elements from the FIFO stack. The ports operate in separate clock domains. A synchronization circuit coordinates the read and write operations across the clock domains.Type: GrantFiled: September 28, 1999Date of Patent: October 17, 2000Assignee: National Semiconductor CorporationInventor: Sheung-Fan Wen
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Patent number: 6134144Abstract: A novel flash memory array has an array of memory cells with each memory cell being of a floating gate memory transistor with a plurality of terminals. The memory cells are arranged in a plurality of rows and a plurality of columns, with a word line connecting the memory cells in the same row. A row decoder is positioned adjacent one side of the memory array and is connected to the plurality of word lines for receiving an address signal and for supplying a low voltage signal. A plurality of programming lines are connected to the plurality of rows of memory cells of the array with a programming line connected to the memory cells in the same row. The plurality of programming lines are collinear with but spaced apart from the plurality of word lines and extending only to the row decoder.Type: GrantFiled: September 15, 1998Date of Patent: October 17, 2000Assignee: Integrated Memory Technologies, Inc.Inventors: Tien L. Lin, Ben Yau Sheen
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Patent number: 6134198Abstract: A tracking error signal calculation circuit has peak detection multiplication circuits which detect the peaks of the detection signals of left and right regions of a photodiode and multiply a coefficient for detecting the deviation of the beam light with respect to the track of the disc recording medium, subtraction circuits for removing an offset by subtracting these multiplication results from the detection signals, and a subtraction circuit which calculates a difference of the signal obtained by removing the offset (performs push-pull operation) and outputs a tracking error signal. The value of the coefficient can be changed by adding an alignment signal to the detection signal. In order to impart the frequency dependency to this coefficient, the alignment signal is added to the signal through a filter.Type: GrantFiled: September 8, 1997Date of Patent: October 17, 2000Assignee: Sony CorporationInventors: Etsufumi Yamamoto, Yoshihiro Kobayashi