Abstract: A pipelined arbitration mechanism allows a routing control decision to be effected for a later packet while a current packet is being transferred. The later packet can be issued a fixed number of cycles after the current request. The mechanism has particular advantages when used with a plurality of functional modules connected to a packet router, whereby a single functional module can generate a current request relating to a current packet and a deferred arbitration request relating to a later packet to be issued a fixed number of cycles after the current request.

Abstract: An E2PR4 Viterbi detector receives a signal that represents a sequence of values, the sequence having a potential state. The detector includes a recovery circuit that recovers the sequence from the signal by identifying the surviving path to the potential state and simultaneously adding a modified branch metric to the path metric of the surviving path. By simultaneously identifying the surviving path and adding a modified branch metric to its path metric, such an E2PR4 Viterbi detector can operate faster than a conventional add-compare-select E2PR4 Viterbi detector.

Abstract: A contact is formed within an active region of a substrate at the edge of a die, preferably within the first metallization level in the active region of the substrate. An opening having sloped sidewalls is then etched into the back side of the substrate, exposing a portion of the active region contact. An interconnect is formed on the opening sidewall to connect the active region contact with a die contact pad on the backside surface of the substrate. The active region contact preferably spans a boundary between two die, with the opening preferably etched across the boundary to permit inter-connects on opposing sidewalls of the opening to each contact the active region contact within different die, connecting the active region contact to die contact pads on different dice. The dice are then separated along the boundary, through the active region contact which becomes two separate active region contacts.

Abstract: In a semiconductor device, a method for reducing the effect of crosstalk from an aggressor line to a victim line begins with sensing the occurrence of a voltage change on the aggressor line that can induce a voltage pulse having a pulse magnitude that exceeds a pulse threshold on the victim line. The induced voltage pulse is counteracted by coupling the victim line to a counteracting voltage source. After a predetermined delay period, the coupling of the counteracting voltage source is removed from the victim line. The voltage change on the aggressor line my be sensed from a node connected to either the aggressor line or the victim line. A rising induced pulse is counteracted by coupling the victim line to a more negative voltage source, and a falling induced pulse is counteracted by coupling the victim line to a more positive voltage source.

Abstract: There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, though only the branching cluster is operable to perform branch address computations. The remote conditional branching control circuitry, which is associated with each of the clusters, is operable in response to sensing a conditional branch instruction in a non-branching cluster to (i) cause the branching cluster to compute a branch address and a next program counter address,(ii) cause the non-branching cluster to compute a branch condition, and (iii) communicate the computed branch condition from the non-branching cluster to the branching cluster. The data processor then uses the computed branch condition to select one of the branch address or the next program counter address.

Abstract: A method and system for routing network-based data arranged in frames is disclosed. A host processor analyzes transferred bursts of data and initiates an address and look up algorithm for dispatching the frame to a desired destination. A shared system memory existing between a network device, e.g., an HDLC controller, working in conjunction with the host processor, receives data, including any preselected address fields. The network device includes a plurality of ports. Each port includes a FIFO receive memory for receiving at least a first portion of a frame. The first portion of the frame includes data having the preselected address fields. A direct memory access unit transfers a burst of data from the FIFO receive memory to the shared system memory. A communications processor selects the amount of data to be transferred from the FIFO receive memory based on the desired address fields to be analyzed by the host processor.

Abstract: A priority encoder can be used for a Content-Addressable Memory (CAM) device that typically has an array of CAM cells arranged in columns and rows with each row having a match signal indicative that compare data has matched data within the respective row. A priority encoder is operatively connected to the array of CAM cells and determines a highest priority matching address for data within the array of CAM cells. The priority encoder includes match lines associated with respective rows and precharged bus lines connected into respective match lines that are discharged whenever there is a match signal such that the highest precharged bus line discharged results in an encoded address.

Abstract: A bonding pad arrangement for an integrated circuit includes a bonding pad fabricated on a bonding area to enable bonding. A first ESD resistor is fabricated adjacent the bonding area, and at least a second ESD resistor is fabricated adjacent the first ESD resistor and the bonding area. The bonding pad extends beyond the bonding area to connect to the first ESD resistor and to the at least second ESD resistor, thereby providing at least two input ESD circuits for at least one current consuming electronic circuit from the single bonding pad.

Abstract: A fully automated ASIC style domino synthesis flow is provided for mapping a digital logic design onto a domino logic library. The input to the flow is the same as for standard static synthesis environments and includes an RTL description of the design to be synthesized and a set of timing and physical constraints. The unate step includes reading the design and initializing, simplifying the logic, marking inversions, marking binate cones for duplication, identifying endpoints, performing a reverse traversal, an optional phase optimization, committing netlist changes, primary inputs processing, primary outputs processing, and a final check and save.

Abstract: An image matching method and system for use with multiple images of a scene captured from different angles. Image matching is performed by identifying a plurality of segments within at least two images, determining an initial disparity values for pixels in the images and then determining initial disparity planes for the segments by fitting a plane to initial disparity values for the segments. A refined disparity plane set is created by iteratively refitting the disparity planes by using various fitting cost functions and weighted linear systems. A labeling of each segment to a disparity plane is made by minimizing a global energy function that includes energy terms for segment to disparity plane matching as well as penalizing disparity plane discontinuities between adjacent image segments.

Abstract: An integrated circuit for a smart card in accordance with an exemplary embodiment includes a transceiver and a processor for communicating with a host device via the transceiver and performing a plurality of smart card applications. Moreover, the processor may cooperate with the host device to perform an enumeration based upon at least one default descriptor, and generate a look-up table for allocating data to respective smart card applications based upon the enumeration. Furthermore, the processor may also detect a system event and, responsive to the system event, cooperate with the host device to perform a new enumeration based upon at least one alternate descriptor and generate a new look-up table based thereon.

Abstract: A gigabit ethernet line driver includes a transmitter having both transmitter and active hybrid outputs. The transmitter consists of a plurality of transmitter clusters each connected to both the transmitter and active hybrid outputs. Each transmitter cluster includes a plurality of transmitter cells consisting of a driver cell and digital to analog converter connected to driver cell. A hybrid circuit connects between the transmitter outputs and receiver inputs for separating a receiver signal from the transmitter signal responsive to a tuning signal.

Abstract: A battery protection structure is described. The structure provides battery overcharging protection while allowing for minimal battery voltage drop during normal battery operation. One resistance element sets voltage drop during normal operation, and the sum of two resistance elements sets the maximum battery charging current which will be allowed. The structure provides protection against single component failures.

Abstract: A large diameter glass wafer is pattern-etched to provide a plurality of elongated lens elements arranged side-by-side, the etching leaving small rods in place to keep the lens elements connected to the wafer during mirror processing. The etching provides curved surfaces for lenses and flat surfaces for mirrors. The mirrors are formed by selectively depositing reflective material on the flat surfaces. The reflective material may comprise an oxide, nitride, sulfide, or fluoride of a transition metal. The flat surfaces that define the mirrors are disposed at angles to the longitudinal dimension of each lens element. In use in an optical disc system, light from a laser diode is reflected by the mirrors and directed at an optical disc through a first lens. Light returns from the disc on a parallel path through a second lens, passes through the lens element, and is directed at a photodetector. The system may include an elongated base element attached to each lens element.

Abstract: A fluorescent lamp assembly includes a fluorescent lamp ballast capable of detecting at least one of a plurality of input signals and generating an output signal. The output signal is associated with a power level that is based on the at least one detected input signal. The fluorescent lamp assembly also includes a fluorescent lamp capable of receiving the output signal and generating light. An intensity of the light is based on the power level associated with the output signal.

Abstract: A thermally-enhanced ball grid array package structure is provided that includes an integrated circuit chip, a heat spreader and a substrate. The integrated circuit chip has a specified surface area. The heat spreader is coupled to the integrated circuit chip. The substrate is coupled to the heat spreader. The substrate has a specified surface area. The heat spreader covers a specified portion of the surface area of the substrate that is greater than the surface area of the integrated circuit chip. The heat spreader is operable to dissipate heat from the integrated circuit chip over the specified portion of the surface area of the substrate.

Abstract: An integrated circuit die having an active area that must remain exposed after packaging is secured by a compliant die attachment by which the integrated circuit die is held in position within a transfer mold during encapsulation. The compliant die attachment may comprise a flexible, compressible tape having pressure-sensitive adhesive, alone or with a rigid substrate support, or a compliant adhesive preferably applied only around a periphery of the die attach area. Deformation of the compliant die attachment under mold clamping pressure allows complete contact of the mold with the active area, preventing bleeding of the encapsulating material under the edge of a mold portion onto the active area.

Abstract: A prior art direct back EMF detection method synchronously sampled motor back EMF during PWM “off” time without the need to sense or re-construct the motor neutral in a sensorless brushless DC (BLDC) motor drive system. Since this direct back EMF sensing scheme requires a minimum PWM “off” time to sample the back EMF signal, the duty cycle cannot reach 100%. Also in some applications, for example, high inductance motors, the long settling time of a parasitic resonant between the motor inductance and the parasitic capacitance of power devices can cause false zero crossing detection of back EMF. An improved direct back EMF detection scheme samples the motor back EMF synchronously during PWM “on” time at high speed. In the final system the motor back EMF can be detected during PWM “off” time at low speed, and it is detected during PWM “on” time at high speed.

Abstract: A testable, prechargeable circuit has a driving circuit for producing a driving circuit output signal. A timing circuit receives a clock signal and the driving circuit output signal to cause an output of the testable, prechargeable circuit to be in a low state when the clock signal is low. The timing circuit also causes the output of the circuit to be timed with a state change in the clock signal to provide a domino logic output signal. Either a data signal or a test signal are multiplexed to the input of the driving circuit to produce respectively the domino logic output signal or a test output signal. A static logic circuit receives the test output signal to produce a test signal output.

Abstract: A receiver for high-speed data communications, which receives a differential signal through a pair of signal lines. The receiver includes a common-mode choke, which has first and second signal windings, which are respectively coupled in series to the pair of signal lines so as to attenuate common-mode interference in the differential signal. The choke also has a sampling winding, which is inductively coupled to the signal windings so as to generate a sampled signal responsive to current flowing in the signal windings. Signal processing circuitry is coupled to receive the sampled signal from the sampling winding and to receive the differential signal from the signal windings and to process the differential signal responsive to the sampled signal.