Abstract: A servo circuit includes a servo channel and a processor. The servo channel recovers servo data from servo wedges that identify respective data sectors on a data-storage disk. The processor detects one of the servo wedges on spin up of the disk, i.e., while the disk is attaining or after the disk attains an operating speed. By detecting a servo wedge instead of a spin-up wedge to determine an initial head position on disk spin up, such a servo circuit allows one to increase the disk's storage capacity by reducing the number of, or altogether eliminating, spin-up servo wedges from the disk.

Abstract: A first order phase-locked loop includes a tuning circuit which allows phase lock to be quickly reached, and to be maintained during transient situations such as loss of the data signal. Such an improved circuit has a tuning circuit for the voltage controlled oscillator which utilizes two capacitors. Two signals are used to drive a first, larger, capacitor, and have the same duty cycle when the capacitor voltage is proper and the voltage controlled oscillator is operating at the correct frequency. A second, smaller, capacitor is used to quickly achieve phase lock with the incoming data signal. The use of two oppositional signals to drive the capacitors allows them to more quickly be charged or discharged to the proper voltage level to obtain both frequency and phase lock with the incoming data signal. Thus, the circuit is able to quickly acquire lock during power-up, or reacquire lock under circumstances where the operating condition of the circuit changes suddenly.

Abstract: A write driver for driving a write current through a write head connected to the write head by an interconnect or flexible transmission line. The write driver includes a circuit matching an output impedance of the write driver to the odd characteristic impedance of the interconnect and includes a current source generating a current output to the write head. The write driver provides a current amplification effect as the output current is half the write current driven through the write coil. The impedance matching circuit includes an output resistor with a resistance equal to the odd characteristic impedance of the interconnect. The write driver includes a voltage source that operates to maintain a voltage drop of zero on the output resistor during the initial period of twice the transmission delay of the interconnect.

Abstract: An apparatus includes a plurality of macrocells formed from logic capable of performing one or more functions. The apparatus also includes a clock tree capable of receiving a clock signal and providing at least one copy of the clock signal to each macrocell. The clock tree includes a local branch within each macrocell, where each local branch is capable of providing at least one copy of the clock signal. In addition, the apparatus includes at least one glitch detection circuit capable of detecting a glitch in one or more copies of the clock signal provided by the local branches in the macrocells.

Abstract: An integrated circuit (IC) may include at least one smart card memory for storing a set of default requests and at least one alternate request for each default request. The IC may further include a microprocessor connected to the at least one smart card memory for communicating with a host device using the default requests and alternate requests. The microprocessor may selectively switch between using the default requests and the alternate requests when communicating with the host device. As such, this provides a “moving target” which makes it difficult for would-be hackers to determine which requests are used for which smart card operations and, thus, to decipher and interfere with data communications.

Abstract: A secure device includes a memory capable of storing information. The secure device also includes a secure microcontroller capable of securing the information in the memory. The secure microcontroller includes a plurality of registers. The secure microcontroller also includes combinatorial logic capable of receiving at least one output value provided by at least one of the registers. The combinatorial logic is also capable of performing one or more combinatorial operations using the at least one received output value. In addition, the secure microcontroller includes dummy cycle circuitry capable of causing one or more of the registers and the combinatorial logic to change state and consume current during one or more dummy cycles.

Abstract: A slew rate control circuit includes a receiver for receiving input signals and an output generator for generating output signals based on the input signals. The slew rate control circuit also includes an electrical interconnection coupling an output of the receiver and an input of the output generator. In addition, the slew rate control circuit includes a voltage clamp for clamping a voltage on the electrical interconnection between two known voltage reference levels. The voltage clamp may include a first current source for providing driving capacity to a driver circuit to prevent the voltage on the electrical interconnection from falling below one known voltage reference level. The voltage clamp may also include a second current source and a third current source for providing sinking capacity to the driver circuit to prevent the voltage on the electrical interconnection from rising above the other known voltage reference level.

Abstract: A protective barrier layer, formed of a material such as titanium or titanium nitride for which removal by chemical mechanical polishing (CMP) is primarily mechanical rather than primarily chemical, formed on a conformal tungsten layer. During subsequent CMP to pattern the tungsten layer, upper topological regions of the protective barrier layer (such as those overlying interlevel dielectric regions) are removed first, exposing the tungsten under those regions to removal, while protective barrier layer regions over lower topological regions (such as openings within the interlevel dielectric) remain to prevent chemical attack of underlying tungsten. CMP patterned tungsten is thus substantially planar with the interlevel dielectric without dishing, even in large area tungsten structures such as MOS capacitor structures.

Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row.

Abstract: A matrix H for encoding data words is defined for wide word ECC with uniform density and a reduced number of components. The H-matrix is incorporated in an encode unit operable to Hamming encode a data word with a 10×528 matrix generated in groups of four columns wherein; a first column is a complement of a second column; the value of the second column ranges from 9 to 271 in increments of two; a third column is a complement of a fourth column; and the value of the fourth column is the same as the value of the second column less one; and wherein a 528-bit bottom row is added to the 10×528 matrix comprising alternating zeroes and ones starting with a zero creating an 11×528 matrix.

Abstract: A very long instruction word processor with sequence control. During each cycle the processor generates control signals to functional units based on the values in fields of an instruction. Each instruction may include an iteration count specifying the number of cycles for which the control signals should be generated based on that instruction. The instruction set further includes flow control instructions allowing for repetitive execution of a single instruction, repetitive execution of a block of instructions or branching within a program. Such a processor is illustrated in connection with a disk controller for a hard drive of a computer. The flexible sequencing allows a hard-drive controller to be readily reprogrammed for use in connection with different types of media or to be dynamically reprogrammed upon detection of a disk read error to increase the ability of the disk controller to recover data from a disk.

Abstract: An automatic method for assigning the clock phases on a domino datapath embedding static gates includes replacing domino cells on non-critical paths by a static equivalent cell, delaying the clock arrival on domino gates driven by static signals, ensuring that critical data never waits for the clock in the domino pipeline, ensuring that a domino data never goes to precharge, and therefore is lost before it is consumed, ensuring that the domino datapath operates at any speed below the maximum operating speed, ensuring that domino signals leaving the design through primary outputs of a static block are latched to prevent the precharge to overwrite the evaluated results, providing an optimal solution in terms of performance, area and power, defining some constraints that are checked and enforced by the downstream tools in order to guaranty the proper functionality of the design.

Abstract: A voltage translating control structure for switching logic is described. A battery drain problem is corrected by this structure. The voltage translating feature allows reliable switching between power supply and battery even if the power supply voltage has significantly decreased. Operation is adaptable to include all DC power systems. Logic circuitry that also allows voltage translation is presented.

Abstract: An emulator for a multi-mode smart card may include emulation circuitry for performing smart card applications in a plurality of operational modes. The emulator may also include a smart card connector to be connected to a smart card adapter operable in at least one of the plurality of operational modes. The smart card connector may include a plurality of contacts. Moreover, the emulator may further include a plurality of cable assemblies having first ends connected to the emulation circuitry, where each cable assembly is for a respective operational mode. Further, the emulator may also include an interface device connected between second ends of the plurality of cable assemblies and the smart card connector for selectively electrically connecting a selected cable assembly to predetermined ones of the contacts of the smart card connector based upon the at least one operational mode of the smart card adapter.

Abstract: Step 2 demodulation is conventionally performed using a secondary synchronization channel that correlates a received signal at a known time slot location against each of a plurality of sequences associated with the secondary synchronization code. The disclosed implementation proposes the use of a different synchronization channel to complete the step 2 process. More specifically, a complete synchronization channel correlator is used for the demodulation where the received signal at the known time slot location is correlated against a combination of the primary synchronization code and each of the plurality of secondary synchronization codes. This combined correlation produces enhanced step 2 performance in terms of acquisition time or signal-to-noise ratio.

Abstract: A coprocessor executing one among a set of candidate kernel loops within an application operates at the minimal clock frequency satisfying schedule constraints imposed by the compiler and data bandwidth constraints. The optimal clock frequency is statically determined by the compiler and enforced at runtime by software-controlled clock circuitry. Power dissipation savings and optimal resource usage are therefore achieved by the adaptation at runtime of the coprocessor clock rate for each of the various kernel loop implementations.

Abstract: A sensing circuit determines whether an integrated circuit is currently exposed to one of a relatively low or a relatively high temperature. A selection circuit selects a measured voltage across the base-emitter of a bipolar transistor if the sensing circuit indicates that the circuit is exposed to the relatively low temperature or, alternatively, selects a measured delta voltage across the base-emitter of the bipolar transistor if the sensing circuit indicates that the circuit is exposed to the relatively high temperature. A comparator compares the selected measured voltage against a first reference voltage indicative of a too cold temperature condition or compares the selected measured delta voltage against a second reference voltage indicative of a too hot temperature condition. As a result of the comparison, detection may be made as to whether the integrated circuit is currently exposed to a too cold or too hot temperature.

Abstract: A circuit and method are disclosed for monitoring the state of at least one switch. The circuit may include a first circuit, coupled to a switch, for detecting whether the switch is in one of a closed state and an open state and generating a signal having a value based upon the detection. The circuit may further include a second circuit, coupled to the first circuit, for configuring the first circuit to selectively detect the switch switching from a normally open state and to selectively detect the switch switching from a normally closed state.

Abstract: Circuits and methods for supplying a temporary power supply at a predetermined voltage. A circuit includes a first DC/DC voltage converter that receives an input from a power supply at a first voltage level and generates an output at a second voltage level, higher than the first voltage level. The output is provided to charge a capacitor. A second DC/DC voltage converter has an input connected to the capacitor for drawing power from the capacitor at the second voltage level and generating an output voltage less than the second voltage level. The second DC/DC voltage converter further includes a feedback input that monitors the circuit's output voltage and activates the second DC/DC voltage converter when the output voltage falls below a predetermined threshold.

Abstract: An integrated circuit structure and method provides for an integrated circuit device to respond to an edge transition detection (ETD) pulse in one of two ways. First, in response to the ETD pulse, the integrated circuit device exits a test mode at least temporarily every cycle of the integrated circuit device. Second, a node of the integrated circuit device is re-initialized every cycle if it is not forced by a super voltage indicative of test mode entry. Both of these responses prevent accidental entry of the integrated circuit device into the test mode. If the integrated circuit device is supposed to be in the test mode, it stays in the test mode. If, however, the integrated circuit device is not intended to be in the test mode, the ETD pulse forces the integrated circuit device out of the test mode. Subsequent entry into the test mode of the device is permitted if conditions for entry into the test mode have otherwise been met.