Abstract: A method and apparatus control bit rates used in a moving pictures encoder, such as an MPEG standard encoder. A sequence of moving pictures is divided into segments each of which comprises one or more groups of pictures. A constant overall bit rate is specified for the sequence of pictures, but variable bit rate encoding used within each segment. A difference between the number of bits allocated for encoding the segment and the actual bits used for encoding is determined, and the difference distributed over one or more subsequent segments.

Abstract: An improved superscalar processor. The processor includes multiple lanes, allowing multiple instructions in a bundle to be executed in parallel. In vector mode, the parallel lanes may be used to execute multiple instances of a bundle, representing multiple iterations of the bundle in a vector run. Scheduling logic determines whether, for each bundle, multiple instances can be executed in parallel. If multiple instances can be executed in parallel, coupling circuitry couples an instance of the bundle from one lane into one or more other lanes. In each lane, register addresses are renamed to ensure proper execution of the bundles in the vector run. Additionally, the processor may include a register bank separate from the architectural register file. Renaming logic can generate addresses to this separate register bank that are longer than used to address architectural registers, allowing longer vectors and more efficient processor operation.

Abstract: The invention relates to a data modulation method applicable to make data streams tend to have desired properties, useful for clock recovery, making signals more distinguishable, or enforcing run-length conditions. A stream of input data and a corresponding stream of output data are grouped into elements of a finite field. Input elements of said input data are modified by a transform generating output elements of the output data, such that a current output element is a linear combination of a current input element and at least one previous output element. A multiplier applied to at least one previous output element is a non-zero and non-unity element of the finite field. A set of initial conditions inherent to the transform, is selected such that the output elements resulting from the transform tend to have the desired property.

Abstract: An audio signal switch has a plurality of inputs and an output. Each input is arranged to be selectively connected to the output via a respective transmission chain, each transmission chain includes: a first bipolar transistor, of a first type, connected to the input; a second bipolar transistor, of a second type, complementary to said first configuration, connected to the output; and an intermediate bipolar transistor, of the second type, connected between said first and second transistors. The first and second transistors are arranged in an emitter-follower circuit configuration, and the intermediate transistor is arranged to act as a diode to protect the first transistor from a large reverse voltage applied to its base-emitter junction.

Abstract: A method includes generating an output signal at a transmitter using an input signal. The method also includes providing the output signal for communication over a communication link. The method further includes identifying a return signal by at least partially removing from the output signal at least one of: the communicated signal and base line wander. In addition, the method includes establishing a synthesized impedance to the return signal.

Abstract: A system and method is disclosed for increasing the strength of a bond made by a small diameter wire in ball bonding. In one embodiment of the invention a structure for receiving a ball bond comprises substrate material that has portions that form a substrate cavity and a wire bond pad that covers and fills the substrate cavity. The wire bond pad also has portions that form a wire bond cavity for receiving the ball bond. The ball is wirebonded to the sides and bottom of the wire bond cavity. The sides of the wire bond cavity provide additional strength to the bond to resist shear and tensile forces that may act on the wire.

Abstract: An apparatus and method are provided to accelerate error diffusion for color halftoning for embedded applications. High performance is achieved by utilizing functional parallelism within the halftoning error diffusion process, including exploiting data parallelism in different color planes, reducing the number of memory accesses to the error buffer, accelerating the computation by using a parallel instruction set, and improving the throughput of the system by implementing pipelined architecture. A halftoning coprocessor architecture can implement the foregoing. The architecture can be optimized for high performance, low complexity and small footprint. The coprocessor can be incorporated into embedded systems to accelerate the performance of error diffusion halftoning therein.

Abstract: A radio frequency digital-to-analog converter with a programmable current output. In exemplary aspects of the invention, improved apparatus and methods for providing (i) current mirror matching, (ii) enhanced current pulse rising edge performance, (ii) reduced base voltage swing, and (iv) compensated high voltage swing, are provided. The foregoing apparatus and methods can be applied to any RF signal application (wireless or otherwise), including for example wireless cellular handsets.

Abstract: A circular buffer storing packets for processing by one or more network processors employs an empty buffer address register identifying where a next received packet should be stored, a next packet address register identifying the next packet to be processed, and a packet-processing address register within each network processor identifying the packet being processed by that network processor. The n-bit addresses to the buffer are mapped or masked from/to the m-bit packet-processing address registers by software, allowing the buffer size to be fully scalable. A dedicated packet retrieval instruction supported by the network processor(s) retrieves a new packet for processing using the next packet address register and copies that into the associated packet-processing address register for use in subsequent accesses. Buffer management is thus independent of the network processor architecture.

Abstract: A multi-tone synchronous collision resolution system permits communication nodes within a MANET to contend simultaneously for a plurality of available channels. The communication nodes contend for access using a synchronous signaling mechanism that utilizes multiple tones in a synchronous manner to resolve contentions. Contentions are arbitrated locally, and a surviving subset of communication nodes is selected. The communication nodes of the surviving subset then transmit data packets simultaneously across the available communication channels.

Abstract: A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner silicides with less likelihood of delamination or metal oxidation may thus be formed.

Abstract: In a method for driving electronic devices connected to a vehicle trailer tow connector a trailer electronic device control signal is receiving from a vehicle data communication network. In response to the received control signal, a solid state power control device is switched to connect electrical power to a selected pin of the trailer tow connector. The trailer electronic device control signal may be received from a wiring harness connector connected to a vehicle data communication network. A vehicle trailer tow connector module includes a module housing. A vehicle wiring connector and a trailer wiring connector are coupled to the module housing. A power control circuit is connected to a selected pin in the trailer wiring connector. A controller circuit is coupled to the vehicle wiring connector for receiving communication data from a vehicle data bus, and coupled by control lines to the power control circuit.

Abstract: A WLAN communication system and algorithm that adaptively changes the data transmission rate of a communication channel based on changing channel conditions. The WLAN communication system or algorithm has two modes being a searching mode and a transmission mode. Furthermore, the WLAN communication system or algorithm incorporates an additive increase, multiplicative decrease (AIMD) function into the rate adaptation algorithm.

Abstract: A calibrator circuit and method for VCOM voltage adjustment for an LCD includes using integrated programmable resistive arrays. The method uses two DACs and three integrated circuit arrays to provide all of the advantages of VCOM calibrator circuits using external resistive voltage-dividers. The integrated circuit resistor arrays reduce the number of external components and PCB space. The method used is suitable for higher resolution adjustment of the VCOM voltage and no calculation is required in the whole adjustment procedure, which saves labor cost, time and enables automation of the calibrator fabrication.

Abstract: A driver for a DC-to-DC converter that may utilize a flyback or buck-boost converter circuit. The driver includes a driver circuit and an interface circuit. The interface circuit has a sensor sensing an input voltage from a DC supply and generating a sensor signal to a driver selector. The driver selector compares the sensor signal to a comparison voltage to determine the type of converter circuit and then transmits a selector signal to a driver circuit where it is used to control one or more of the components of the driver circuit, such as the logic circuit which is used for driving the converter to regulate the converter output. The sensor includes a sense resistor along with a current-sense amplifier, which is adapted for connection to a high side or a low side of a power supply while still producing a substantially equivalent output voltage or sensor signal.

Abstract: A semiconductor indicator for quantitatively diagnosing voltage conditions in high power transistor devices is provided. The semiconductor indicator includes a first transistor and a second transistor, where an electrically active periphery of the second transistor is less than an electrically active periphery of the first transistor. The transistors are thermally coupled to one another and may be in close proximity. The second transistor detects the voltage of a node on the first transistor and may be monitored by infrared imaging. The breakdown voltage characteristic of the second transistor may not substantially change as the temperature in the first transistor increases. An optional control circuit monitors and detects the output voltage of the first transistor.

Abstract: A gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.

Abstract: A comparison is made in a number of scenarios of a current channel gain setting for a receiver to a threshold. If the current channel gain setting is less than the threshold, then current within at least a portion of the receiver is decreased. In one scenario, the comparison is only made in event that no single tone interferer is detected. In another scenario, the comparison is made to a tolerable single tone blocker threshold, and if greater then current is decreased. In another scenario, the comparison is made to an acceptable intermodulation response rejection threshold, and if greater then current is decreased. In yet another scenario, the comparison is made to an acceptable spurious free dynamic range threshold, and if greater then current is decreased. The portions of the receiver for which current decreases are implemented include a low noise amplifier, mixer, voltage controlled oscillator and variable gain amplifiers.

Abstract: A system and method is disclosed for controlling a height and a planarity of an integrated circuit die. In one advantageous embodiment of the invention, a plurality of patterned metal stops are fabricated on an integrated circuit substrate and covered with die attach material. An integrated circuit die is inserted into the die attach material and placed into a clamping mechanism of a molding machine. The clamping mechanism (1) compresses the die into the die attach material, (2) rotates the die into parallel alignment with the substrate, and (3) pushes the die into contact with the patterned metal stops. In this manner the die height and the die planarity are precisely controlled.

Abstract: An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node.