Abstract: A method and apparatus for a data processing system for accessing classes and methods in an object oriented system. Responsive to receiving a selected user input to a container, a view event is sent from a view controller to an application mediator. The view event identifies an action taken to generate the selected user input. A request is selectively generated based on the view event, wherein the request event includes a major code identifying a class name as a destination and a minor code identifying a method name a function to be invoked. The request event is sent to a transporter. The transporter acts as a router to send the request event to an appropriate destination object from a plurality of destination objects. Responsive to receiving the request event at the transporter, the request event is sent to a destination object within a plurality of destination objects based in the class name.

Abstract: A method, apparatus and program for dynamically allocating addresses to computer devices connected to Inter Integrated Circuit (I2C) buses are provided. Upon resetting a I2C bus, the invention uses a bus driver to turn on the first bus switch on the bus. The invention then accesses the first device downstream of the switch and allocates a new value to the device's address. The invention proceeds to turn on the next switch downstream. A new address is then allocated to the device downstream from the second switch. This process continues until all of the devices connected to the bus have unique addresses.

Abstract: A data processing system, method, and computer program product for automatically tracking insertions of integrated circuit devices into receptacle devices. An insertion of an integrated circuit device is automatically detected utilizing the data processing system. An insertion count that is associated with the integrated circuit device is automatically incremented in response to a detection of an insertion of the integrated circuit device. The insertion count is used to track insertions of the integrated circuit device.

Abstract: A method, system, and computer product are disclosed for improving wireability near clock nets in a logic design that includes multiple logic blocks. Each of the logic blocks has an actual physical size. Logic blocks that are a particular type are identified. During placement of the logic blocks, an apparent physical size of each of the identified logic blocks is utilized as a physical size for the identified logic block. The apparent physical size is larger than the actual physical size. During routing, the actual physical size of each of the identified logic blocks is utilized.

Abstract: A bus switch module for use in a bus such as an I2C bus is provided. In one embodiment, the switch module includes a control unit and a switch. The control unit includes an input for receiving instructions from a bus driver as to whether to close or open the switch. The switch includes a first and a second data connection which connect the switch to a first and a second segment of the bus and includes a control input for receiving commands from the control unit. The control unit opens and closes the switch in response to instructions received from the bus driver and signals received in the first data connection are passed to the second data connection only when the switch is closed in response to a command from the control unit.

Abstract: A method, system and apparatus for instruction tracing with out of order speculative processors. With the present invention, information corresponding to the state of an instruction cache and a data cache is stored in a trace storage device along with information corresponding to instructions fetched by the processor. When a cache load is necessary, updated cache information is stored in the trace storage device. Thereby, the state of the cache at all times during fetching of instructions may be known from the information stored in the trace storage device. Additionally, the particular instructions fetched is known from the fetched instructions information stored in the trace storage device. Hence the instruction stream may be reconstructed from the information stored in the trace storage device.

Abstract: A method, program and system for associating memory windows with memory regions in an infiniband data storage system are provided. The invention comprises registering a Memory Region, wherein the Memory Region is a set of virtually contiguous memory addresses defined by a virtual address and length. The system then establishes and maintains a Window Reference Count (WRC) for the Memory Region, which tracks the number of Memory Windows which are bound to the Memory Region. When the system binds a Memory Window to the Memory Region, the value of the WRC is incremented. When a Memory Window is unbound from the Memory Region, the value of the WRC is decremented. If no Memory Windows are bound to the Memory Region, the value of the WRC is zero. The Memory Region is not deregistered unless the value of the WRC equals zero.

Abstract: A system and method are disclosed for visually indicating a usage of a magnetic tape that is included in a magnetic tape cartridge. The apparatus includes a take-up spindle for receiving magnetic tape when the magnetic tape is moving in a forward motion. The apparatus also includes a meter assembly having a meter coupled to the take-up spindle. In a first embodiment, the meter is incremented only in response to each full rewind of the magnetic tape. In a second embodiment, the meter is incremented in an amount that is directly proportional to the amount of each rewind of the tape.

Abstract: A user may easily select a desired day and month in an electronic calendaring system. The user selects a number representing the desired day from a calendar displayed by the electronic calendaring system. The user is then automatically presented with a list of all the months of a year. The user then selects the desired month from the list, and the user is presented with a visual representation of the desired day and month. The user may select the number representing the desired day by right clicking with a pointing device. Additionally, the automatic presentation of a list of all the months of a year may comprise presenting the user with a pop-up menu.

Abstract: A data structure to aid in and a method, system, and computer program product for prefetching data from a data cache are provided. In one embodiment, the data structure includes a prediction history field, a next line address field, and a data field. The prediction history field provides information about the success of past data cache address predictions. The next line address field provides information about the predicted next data cache lines to be accessed. The data field provides data to be used by the processor. When a data line in the data cache is accessed by the processor, determines the value of a prediction history field and the value of a next line address field. If the prediction history field is true, then the next line address in the next line address field is prefetched. Based on whether the next line actually utilized by the processor matches the next line address in the next line address field, the contents of the prediction history field and the next line address filed are modified.

Abstract: A method, apparatus, and computer program product are described for controlling data transfer. A next data packet to be transferred is retrieved. A determination is made regarding whether a data bus busy signal is asserted. If the data bus busy signal is asserted, a determination is made regarding whether a data bus grant signal is asserted. If the data bus grant signal is asserted, the next data packet is transferred on the next cycle after a last cycle of data transfer of a previous data packet.

Abstract: A method and apparatus in a data processing system for asynchronous context switching. Requests of graphics processes are received to process graphics data for display in a queue in the graphics adapter. A current context is switched for a first graphics process to a new context for a second graphics process only in response to requests received in the queue. In this manner, the graphics adapter is able to continuously process commands in the queue instead of waiting for new commands to be sent after each context switch.

Abstract: A method, system, and computer program product for enforcing logical partitioning of input/output slots within a data processing system is provided. In one embodiment, the system includes a hypervisor and at least one DMA address checking component. The hypervisor receives non-direct-memory-access requests for access to input/output slots and prohibits devices within one logical partition from accessing the input/output slots assigned to a different logical partition. The DMA address checking component receives direct-memory-access requests and prohibits requests for addresses not within the same logical partition as the requesting device from being completed. Requests with addresses corresponding to the same logical partition as the requesting device are placed on the primary PCI bus by the DMA address checking component for delivery to the system memory.

Abstract: A method and apparatus for detecting bits set in a data structure. A first level encoding stage receives bits for the data structure, groups the bits into a set of bit groups, and encodes the set of bit groups to form a set of output bits. A set of intermediate level encoding stages is connected to the first level encoding stage. Each level intermediate encoding stage receives output bits from a previous stage, groups the output bits into a plurality of bit groups, and encodes the plurality of bit groups to generate a plurality of output bits. A final level encoding stage is connected to a last intermediate level encoding stage within the set of intermediate level encoding stages, wherein the final level encoding receives final output bits from a last intermediate level encoding stage within the plurality of intermediate level encoding stages and encodes the final output bits to generate an indication of bits set in the data structure.

Abstract: A method and an apparatus is presented for updating flash memory that contains a write protected code, a first copy of rewritable recovery code, a second copy of rewritable recovery code, and a rewritable composite code. Each block of rewritable code contains a checksum code to detect if the block of code has been corrupted. If it is detected that the first copy of the recovery code is corrupted then the second copy of the recovery code is copied into the first copy of the recovery code. If it is detected the second copy of the recovery code is corrupted then the first copy of the recovery code is copied into the second copy of the recovery code. The recovery code is responsible for checking and updating the composite code. If it is detected the composite code is corrupted then a fresh copy of the composite code is obtained from a removable storage device or a network connection.

Abstract: A process for efficiently computing moments in an interconnected circuit begins by partitioning the circuit into sets of line-like two-port circuits. Next, capacitors are converted to equivalent current sources and inductors are converted to equivalent voltage sources. From a first port, any connected voltage source which is present in line is added to the port voltage source. Then, that voltage source combined with the connected resistor and the Thevenin equivalent circuit is converted to a Norton equivalent circuit. The current source created from the conversion is added to a current source in the circuit and the Norton equivalent circuit is converted back to a Thevenin equivalent circuit. The process is recursively performed until the opposite port is reached. The moment is then computed from the final Thevenin equivalent circuit by using the voltage and current at the port. The Thevenin-Norton-Thevenin recursive process is then repeated for the opposite port.

Abstract: A method and an apparatus is presented for preventing an adapter card that has been reset from issuing spurious error signals due to the fact it is not synchronized with the system at the time it comes out of reset. To prevent spurious errors, the data processing issues a command to the adapter card that is to be reset that disables error checking before the reset command is sent. The reset command is sent next. After the adapter card completes the reset operation, it notifies the system that the reset is completed. The adapter card waits until it receives a command from the system to re-enable error checking before it turns back on error checking. In this manner, the system can insure that error checking is only turned back on synchronously with other system activities so that spurious error signals are not generated.

Abstract: A method, system, and product are described for configuring a computer network. A database is established which includes information about multiple network products. The network products are supplied by multiple different vendors. The computer network is then configured by selecting ones of the network products to implement the computer network. The computer network is thus configured utilizing products available from different vendors. Attributes are established which are used to evaluate network products. Each of the network products are assigned a weighted value for each of the attributes. A selection of network products is made utilizing the attributes and the weighted values assigned to the network products.

Abstract: Repairing arrays on a processor with an on chip built in self test engine on the processor is provided. A subset of the arrays is selected for testing. Data patterns are sent from the test engine to the subset of arrays at a plurality of operating parameters. A response is received at the test engine from the subset of arrays at the operating parameters. The received response is compared to an expected response using the test engine, wherein the processor controller determines if additional test failures were detected by the test engine for the subset of arrays with a plurality of JTAG based instructions. Code in the processor controller then determines the states that need to be scanned into the scannable latches to force the array control logic to choose additional spare wordlines and/or bitlines to repair the newly identified failures in addition to all previously defined repair actions.

Abstract: A method, system, and apparatus for isolating fatal data fetch errors to a single partition within a logically partitioned data processing system. In one embodiment, the logically partitioned data processing system includes a plurality of operating systems and a plurality of processors is provided. Each of the operating systems is assigned to a separate one of a plurality of logical partitions. Each of the processors is assigned to one of the plurality of logical partitions. The logically partitioned data processing system also includes a hypervisor for creating and maintaining separation of the plurality of logical partitions. The hypervisor contains services and functions accessed by each of the logical partitions and, to prevent fatal data fetch errors in one partition from effecting other partitions within the logically partitioned data processing system, the hypervisor includes a plurality of data structure areas.