Patents Represented by Attorney, Agent or Law Firm Loeb & Loeb LLP
  • Patent number: 5966333
    Abstract: A semiconductor memory device includes normal row selection lines (NWL1 to NWL128) for selecting one of normal rows, a spare row selection line (SWL) for selecting a spare row instead when one of the normal rows has a defect, fuses (F1 to F128) which are respectively arranged on the normal row selection lines, and blown when a defect exists, a normal row non-selection circuit (inverters IN3 and IN6 and gate G3) when one of the fuses (F1 to F128) is blown, setting a corresponding normal row in a non-selected state, and a spare row selection circuit (gates G4, G5, and G6, transistors P2 and N1, a NOR gate NR1, and an inverter IN6) selecting the spare row instead of the defective normal row. The spare row selection circuit performs dynamic operation in synchronism with a clock (ck).
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: October 12, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Otani, Yasumitsu Nozawa, Satoru Hoshi
  • Patent number: 5965921
    Abstract: In an integrated circuit type semiconductor device consisting of MISFETs, high rated voltage characteristic is obtained in a gate insulation film structure of a thin film. Further, a reduction in the manufacturing cost of semiconductor devices including high-rated voltage and low rated voltage MISFETs. An intermediate gate electrode is provided which overlies a channel formation region and a gate region with the same gate insulation film being sandwiched therebetween. The gate region is provided on the surface of a substrate. The channel formation region has an impedance indirectly controllable via the intermediate gate electrode upon application of a voltage to the gate region. The intermediate gate electrode is provided with a voltage reset(set) means connected thereto for eliminating the occurrence of charge-up.
    Type: Grant
    Filed: July 17, 1996
    Date of Patent: October 12, 1999
    Assignee: Seiko Instruments Inc.
    Inventor: Yoshikazu Kojima
  • Patent number: 5962373
    Abstract: A precursor is made from a plurality of materials having different vapor pressures. The precursor and a source material are placed in a closed heat treatment furnace. The source material is materials which are the same as some of the materials contained in the precursor and having particular vapor pressures. The precursor and source material is thermally treated in the furnace while the source material is being supplied, so the particular materials in the precursor have their evaporation suppressed, thereby forming compounds. The compounds may be oxide superconductors, oxide dielectric, and so on.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: October 5, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Masaaki Nemoto, Shuichi Yoshikawa, Ryokan Yuasa, Isao Yoshida, Yorinobu Yoshisato
  • Patent number: 5963221
    Abstract: An input video signal is reduced according to size reduction ratio data K in an input processing section and written into alternate field memories. The written reduced video signal is alternately read from the field memories in a display processing section and processed for window displaying. Video reduction control sections are provided on the respective input and display sides, so that various signals, such as RHOLD, ADCANS, RACK signals, etc., are exchanged therebetween. When a size reduction ratio data K is changed, on the display side a read memory is fixed on a first field memory and size data is fixed, while on the write side video data is written into a second field memory, based on the new reduction ratio. After updating the size data on the display side, video data is read from the second field memory at the new reduction ratio.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: October 5, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yutaka Shimizu, Kazunori Chida
  • Patent number: 5963500
    Abstract: A decoder circuit selectively controls the transfer gate group. The transfer gate group is stacked so as to form a tree structure having multiple stages of transfer gates and enable a monitoring bus line to be connected to any column in a memory cell array. This configuration enables the current in each memory cell to be monitored at an external pad via a single bus line, which reduces the area occupied by the bus lines, suppressing an increase in the chip size.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: October 5, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadayuki Taura, Shigeru Atsumi, Hironori Banba
  • Patent number: 5962528
    Abstract: Disclosed herein is method of treating and a composition for treating erectile dysfunction in a male patient by administering to the patient a unit dose of a formulation comprising an erectile dysfunction treating amount of a prostaglandin, namely prostaglandin E.sub.1, prostaglandin E.sub.2, or pharmaceutically acceptable salts or derivatives thereof, wherein the prostaglandin is formulated with a small amount of prostaglandin F.sub..alpha.2 together with a pharmaceutically acceptable delivery medium and/or a lubricant.
    Type: Grant
    Filed: March 11, 1998
    Date of Patent: October 5, 1999
    Inventor: Nathan Earl Scott
  • Patent number: 5958813
    Abstract: The semi-insulating aluminum nitride sintered body of this invention is composed of aluminum nitride particles, electroconductive fine particles having a volume inherent resistivity value of not larger than 10.sup.2 .OMEGA..multidot.cm which are dispersed among the aluminum nitride particles and an intergranular phase formed from an oxide containing at least one element selected from the group consisting of Ti, Ce, Ni, Ta, Y, Er and Yb, or from Si. This sintered body has a volume inherent resistivity value of 10.sup.4 to 10.sup.11 .OMEGA..multidot.cm, and is very useful, for example, as a member for removing static electricity, or a dielectric layer of an electrostatic chuck. Since dispersions of volume inherent resistivity values are very small, a material having a volume inherent resistivity value within a certain range can be produced with good reproducibility. Accordingly, the yield is high, and the productivity is very good.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: September 28, 1999
    Assignee: Kyocera Corporation
    Inventors: Hiroshi Aida, Yumiko Ito, Takero Fukudome, Kazuhiko Mikami
  • Patent number: 5959472
    Abstract: In the constant current drive type driver used for an LVDS (low voltage differential signal) interface, the parasitic capacitance of the package pins is charged and discharged sufficiently at a high speed to secure the high speed signal transmission operation. Further, the AC differential amplitude large enough to be received by the receiver can be obtained. The driver circuit device comprises: a transmit circuit composed of transistors (52, 53, 56, 57) for transmitting a signal by switching the signal current direction flowing through a pair of transmission lines (8, 9) connected between two output terminals (13 and 13B); and a constant current source composed of transistors (54, 75) for controlling the current value of the transmit circuit. In the idle state, only one of the two transistors (54 and 75) of the constant current source is turned on to limit the signal current flowing through the output terminals (13 and 13B).
    Type: Grant
    Filed: January 28, 1997
    Date of Patent: September 28, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsu Nagamatsu, Tadahiro Kuroda
  • Patent number: 5960272
    Abstract: The present invention is to provide a semiconductor integrated circuit having bipolar transistor elements with a reduced isolating distance between adjacent transistors and a reduced collector/substrate capacitance. In the surface of a P-type semiconductor substrate, N.sup.+ type regions are formed serving as buried collector regions of bipolar transistors TR1 and TR2. Between the N.sup.+ type regions, a P-type region for element isolation is provided not in contact with the N.sup.+ type regions. A P-type impurity concentration in the peripheral portions of N.sup.+ type regions is equal to that of the semiconductor substrate. The insulating film serving as an element-isolating layer is provided on the P-type region in contact therewith and thus electrically isolates adjacent bipolar transistors.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: September 28, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazunari Ishimaru
  • Patent number: 5960323
    Abstract: Laser anneal processing of a semiconductor layer is repeated in a number of steps. Grain size is increased using high energy ELA for a first step, and grain sizes are uniformed using ELA with low energy for a later step. As a defective crystallization region occurs in an excessive energy region during the ELA for the first step, in the ELA for the second time, excessive energy is removed and the defective crystallization region is eliminated by reducing the energy to an optimal value, thereby improving the crystallinity of a p-Si layer.
    Type: Grant
    Filed: June 17, 1997
    Date of Patent: September 28, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ken Wakita, Hidenori Ogata
  • Patent number: 5960328
    Abstract: Superimposed FM data is demodulated to digital data. A synchronism reproducing circuit (data block detecting section) detects the front of blocks in the digital data to generate a block head signal (a station change timing signal), which is supplied to a control section of a station selecting microcomputer. When a station selecting key requests a change of the received station, station data corresponding to a requested station is supplied to the control section (a station selecting control section). When the block head signal is inputted after requesting the change of the station, the control section begins to output station change data to a PLL frequency synthesizer in order to change the frequency signal in a front end. This prevents a latter part of a block in received superimposed FM data from being NG data.
    Type: Grant
    Filed: March 26, 1996
    Date of Patent: September 28, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kazuhiro Kimura, Shigeaki Hayashibe, Yutaka Hirakoso, Takahiko Masumoto, Shizuka Ishimura, Toshiyuki Ozawa, Munehiro Suka
  • Patent number: 5957053
    Abstract: There is provided a stamp material comprising a stamp portion and a stock for holding the stamp portion. The stamp portion includes a stamp surface-forming portion for forming a stamp surface therefrom. The stamp portion is removably mounted in the stock. According to another aspect, there is provided a stamp material-setting jig for setting the stamp material in a stamp-making apparatus. The stamp material-setting jig has a mounting recess formed in one surface for mounting the stock therein, and a positioning portion formed in an opposite surface to the one surface for effecting positioning of the stamp material in the stamp-making apparatus.
    Type: Grant
    Filed: August 14, 1997
    Date of Patent: September 28, 1999
    Assignee: Seiko Epson Corporation & King Jim Co., Ltd.
    Inventor: Hitoshi Hayama
  • Patent number: 5956017
    Abstract: There is disclosed an electronic information apparatus comprising an appratus body; display provided to the apparatus body for displaying a data on a screen thereof and a key board having plural input keys and provided at a front side on an upper surface of the apparatus body, the plural input keys being divided into two groups, the groups being spaced with each other, the plural input keys of each group being arranged in plural rows, row arrangement directions of the groups acrossing each other with a predetermined angle, and the group being arranged as to be substatially symmetrical with respect to a center line extending from a front end of the key board to a back end of the key board.
    Type: Grant
    Filed: September 18, 1997
    Date of Patent: September 21, 1999
    Assignee: Seiko Epson Corporation
    Inventors: Shoichi Ishizawa, Kyoichi Ideno
  • Patent number: 5953904
    Abstract: A lock for an engine thrust reverser comprises a latch member (2) that cooperates with a thrust reverser door to keep it closed. An actuator plunger (9) moves longitudinally to cooperate with the latch member (2) to hold it against movement that would allow the door to open. Either a sleeve (12) is located longitudinally on the plunger (9) so that opposite lateral sides thereof are engaged between the latch member (2) and a fixed abutment (13) to hold the door closed, or the plunger controls a pivoted pawl (32) that is loaded in compression by the latch member (2) when under a door-opening load.
    Type: Grant
    Filed: May 22, 1997
    Date of Patent: September 21, 1999
    Assignee: Dowty Boulton Paul Limited
    Inventor: Arthur Derek Mountney
  • Patent number: 5952101
    Abstract: A granular charging agent capable of injecting the electric charge into a material to charge the surface of the material when coming in contact with the material with the application of a voltage to the charging agent, comprising magnetic particles which comprise electroconductive magnetic particles and high-resistivity magnetic particles of which resistivity is higher than that of the electroconductive magnetic particles. A granular charging agent may comprise magnetic particles, each magnetic particle comprising an electroconductive surface portion capable of forming a flow path of electric current and a surface portion with a resistivity higher than that of the electroconductive surface portion. In addition, a method of charging a material such as a photoconductor using the above-mentioned granular charging agent is disclosed.
    Type: Grant
    Filed: July 11, 1997
    Date of Patent: September 14, 1999
    Assignee: Kyocera Corporation
    Inventors: Yasuo Nishiguchi, Yoshio Ozawa, Susumu Kikuchi, Hisashi Mukataka, Shigeki Tsukahara, Shinji Yamane
  • Patent number: 5950444
    Abstract: Since, due to heat flowing from the outside through central conductors of cables or connectors into an electronic circuit that is operated in a state of being cooled to a low temperature, a temperature distribution or local temperature rising occurs in the electronic circuit, a desired characteristic cannot be obtained for the electronic circuit. There is disclosed an electronic apparatus comprising an electronic device accommodated in a vacuum heat insulation housing, provided with an electronic circuit which is cooled to a temperature between 4 K. and 150 K. to operate, and an input/output coaxial connector of which central conductor is hold by a dielectric having a heat conductivity of 10 W/m.multidot.K. or more at the temperature between 4 K. and 150 K.; and cooling means accommodated in the vacuum heat insulation housing, for cooling the electronic device to the temperature between 4 K.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: September 14, 1999
    Assignee: Kyocera Corporation
    Inventor: Yoshinori Matsunaga
  • Patent number: 5952964
    Abstract: A new planar phased array antenna is disclosed having M by N antenna cells with only M+N phase shifters. A grid of M+N feed lines with the M feed lines at a first frequency having a uniquely controllable phase and N feed lines at a second frequency with each feed line having a uniquely controllable phase are provided separating adjacent cells in the matrix. By coupling an antenna element through a mixer to one row and column feed, a phase for each antenna element in the array can be uniquely controlled through a scan, thereby providing a simplified planar array to be implemented as a patch antenna.
    Type: Grant
    Filed: June 23, 1997
    Date of Patent: September 14, 1999
    Assignee: Research & Development Laboratories, Inc.
    Inventor: James K. Chan
  • Patent number: 5951451
    Abstract: The apparatus (10) for fitting lids (18) to a container (50) is disclosed. The apparatus (10) has an applicator (11,30) and a magazine (12) on which a supply of lids (18) is supported. The applicator (10) may be moved relative to the magazine (12) and pressed against the lids (18) to pick up one of the lids. By pressing the applicator into engagement with an open topped container (50) tabs (20) on the lid are bent out of the plane of the lid and the lid is fitted to the container (50).
    Type: Grant
    Filed: January 26, 1996
    Date of Patent: September 14, 1999
    Assignee: L.A.S. Pty. Ltd.
    Inventor: Ross Winston Tisch
  • Patent number: 5953274
    Abstract: Each of memory cells has one MOS transistor including a drain region, a source region, a channel region and a gate electrode. An impurity-introducing area of the channel region is varied in the width direction of the channel region to store data of plural bits in the memory cell.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: September 14, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Iwahashi
  • Patent number: 5952709
    Abstract: A high-frequency semiconductor device contains a semiconductor element in a cavity formed by a dielectric board and a cap. A first high-frequency transmission line connected to the semiconductor element is formed on the surface of said dielectric board in said cavity and a second high-frequency transmission line is formed on the bottom surface of said dielectric board, so that said first high-frequency transmission line and said second high-frequency transmission line are electromagnetically coupled together. In this semiconductor devise in which the first transmission line and the second transmission line are electromagnetically coupled together, the transmission lines need not be passed over the side wall of the cap, and neigther reflection loss or radiation loss takes place on the side wall. Besides, transmission loss of high-frequency signals is caused by neigther through-holes or via-holes, and is effectively suppressed.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: September 14, 1999
    Assignee: Kyocera Corporation
    Inventors: Kenji Kitazawa, Shinichi Koriyama, Mikio Fujii