Abstract: Memory devices and data structures including multiple configuration bitstreams for programming integrated circuits (ICs) such as programmable logic devices (PLDs), thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting configuration bitstreams are stored in a memory device. Test bitstreams associated with the user bitstreams are optionally also included in the memory device. Under the control of a configuration control circuit, the various bitstreams are sequentially loaded into a partially defective IC and tested using an automated testing procedure. When a bitstream is found that enables the design to function correctly in the programmed IC, i.e., that avoids the defective programmable resources in the IC, the configuration procedure terminates.
Abstract: A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second portion non-operational. At a boundary between the two portions, interconnect lines traversing the boundary include a first section in the first portion and a second section in the second portion. The second PLD die includes the first portion of the first PLD die, while omitting the second portion. The interconnect lines extending to the edge of the second die are coupled together in pairs. A software model for both die includes a termination model that omits the pair coupling, adds an RC load compensating for the omitted connection, and (for bidirectional interconnect lines) flags one interconnect line in each pair as being invalid for use by routing software.
October 6, 2008
Date of Patent:
August 16, 2011
Trevor J. Bauer, Jeffrey V. Lindholm, F. Erich Goetting, Bruce E. Talley, Ramakrishna K. Tanikella, Steven P. Young
Abstract: A bus-based logic block for an integrated circuit includes a provision for placing an arbitrary constant onto a data bus in the logic block. An exemplary logic block has multi-bit first and second inputs and a multi-bit output. The logic block includes a multi-bit multiplexer circuit, a multi-bit programmable logic circuit, and a constant generator circuit. The multiplexer circuit has a multi-bit first input coupled to a multi-bit first input of the logic block, a multi-bit second input, and a multi-bit output. The programmable logic circuit has a multi-bit first input coupled to the output of the multiplexer circuit, and a multi-bit output. The constant generator circuit has a multi-bit output coupled to the second input of the multiplexer circuit. Each bit of the logic block may be commonly controlled with all other bits of the logic block.
Abstract: Methods of providing error correction in configuration bitstreams for programmable logic devices (PLDs). While any error correction method can be used, in one embodiment a Hamming code is applied to instructions in the configuration bitstream, while a product code is applied to configuration data. Thus, the higher overhead required for a Hamming code applies to only a few words in the bitstream. The instructions are corrected on receipt of the word that includes the Hamming code, so the instructions are executed correctly even if a transmission error has occurred. However, configuration data can be stored in the configuration memory without correction. With a product code, the exact location of an erroneous bit is not known until the end of the transmission, when a parity word is received. At this time, the PLD can go back and correct erroneous bits in the configuration data prior to enabling the newly loaded design.
Abstract: Methods of implementing circuits while automatically taking multi-cycle paths into account. A processor-implemented method can include inputting a behavioral description of the circuit, a simulation test bench for the circuit, and a library that includes at least one synchronous element. The synchronous element includes code that, when simulated, outputs tracking information including a minimum number of clock cycles between state changes for terminals of the synchronous element. The behavioral description is synthesized to generate a netlist description of the circuit. The netlist description includes at least one instance of the synchronous element. The netlist description is simulated using the simulation test bench and the library. The simulation outputs a description of all multi-cycle paths in the netlist description based on the tracking information output by all instances of the synchronous element in the netlist description.
Abstract: Circuits for implementing logic replication in self-timed integrated circuits are provided. An exemplary circuit includes first and second copies of a replicated circuit, an input circuit, an output circuit, and a pipelined routing path. The first and second copies each have a self-timed input and a self-timed output. The input circuit provides a self-timed input signal alternately to the self-timed inputs of the first and second copies. The output circuit receives the self-timed output from the first copy and the self-timed output from the second copy, and outputs a selected one of the self-timed outputs based on a value of a self-timed select signal. The pipelined routing path routes the self-timed select signal from the input circuit to the output circuit. The number of pipeline stages in the pipelined routing path can be different from, e.g., less than, the number of stages in both the first and second copies.
Abstract: Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting user configuration bitstreams are stored along with associated test bitstreams in a memory device, e.g., a programmable read-only memory (PROM). Under the control of a configuration control circuit or device, the test bitstreams are loaded into a partially defective IC and tested using an automated testing procedure. When a test bitstream is found that enables the associated user design to function correctly in the programmed IC, i.e.
Abstract: Circuits and methods of suppressing signal glitches in an integrated circuit (IC). A glitch on a signal entering a clock buffer, for example, is prevented from propagating through the clock buffer. In some embodiments, a latch is added to an input clock path that detects a transition on the input signal, and then ignores any subsequent transitions for a time delta that is determined by a delay circuit. In some embodiments, a multiplexer circuit is used to select between the input clock signal and the output clock signal, with changes on the input clock signal not being passed through the multiplexer circuit unless the time delta has already elapsed. In some embodiments, the delay is programmable, pin-selectable, or self-adapting.
Abstract: Methods of detecting unwanted logic in a configuration bitstream for a programmable logic device (PLD). The bitstream can be reversed engineered to generate a model of the design. The model is then tested for unwanted logic, e.g., logic inserted for the purpose of monitoring or interfering with the desired functionality of the design, by applying a test suite that exercises all desired functions for the design. If some of the logic nodes in the model are not exercised by the test suite, then the unexercised nodes might constitute unwanted logic and might have been inserted for malicious purposes. To reverse engineer the bitstream, a simulation model of the unprogrammed PLD can be used. Configuration bits from the bitstream can be inserted into the model of the unprogrammed PLD. The modified model can be simplified by propagating constants through the model in response to the values inserted into the model.
Abstract: A programmable logic block provides an improved output delay by bypassing the memory array and multiplexer structure when programmed to function as a random access memory (RAM) and a new value is written to the RAM. A programmable logic block includes memory cells, a multiplexer structure, a memory element, a bypass select multiplexer, and a control circuit. The memory cells implement a RAM driven by a write data input signal and a write enable signal. Each memory cell drives an input terminal of the multiplexer structure. Under the control of the write enable signal, a bypass select multiplexer selects either the write data input signal (in RAM mode) or the output terminal of the multiplexer structure (in another mode), and passes the selected signal to a memory element. Thus, when in RAM mode, write data is simultaneously written to a specified location in the RAM and to the memory element.
Abstract: Computer-implemented methods of generating netlists for use in post-layout simulation procedures. A lookup table includes a predetermined set of features (e.g., transistors of specified sizes and shapes) supported by an integrated circuit (IC) fabrication process, with dimensions and process induced dimension variations being included for each feature. A netlist is extracted from an IC layout, the extracted netlist specifying circuit elements (e.g., transistors) implemented by the IC layout and interconnections between the circuit elements. A search pattern is run on the IC layout to identify features in the IC layout corresponding to features included in the lookup table. Circuit elements in the extracted netlist that correspond to the identified features are then modified using values from the lookup table, and the modified netlist is output. In some embodiments, the netlist extraction, search pattern, and netlist modification are all performed as a single netlist generation step.
May 24, 2007
Date of Patent:
July 27, 2010
Jonathan J. Ho, Yan Wang, Xin X. Wu, Jane W. Sowards
Abstract: Integrated circuits (ICs) having pipelined unidirectional programmable interconnect structures are provided. Substantially similar logic blocks in an IC each include at least one storage element driving an output of the logic block. The IC also includes programmable routing structures, each of which includes at least one storage element unidirectionally driving an output of the routing structure without traversing any pass gates. Each routing structure has at least one unidirectional output that drives another of the routing structures or one of the logic blocks. Each logic block has at least one output that drives an input of a programmable routing structure. The logic blocks and the programmable routing structures may be interconnected by unidirectional data lines organized as multi-bit busses coupled to multi-bit ports of the logic blocks and routing structures. Each routing structure may include a handshake circuit coupled to control all bits in one of the multi-bit busses.
Abstract: A multi-mode circuit for a self-timed integrated circuit is provided. The multi-mode circuit is programmable to operate in two or more modes, and is coupled to require, in each mode, receipt of a token on at least one of first, second, or third inputs before providing an output token. The multi-mode circuit is further coupled to require tokens on different inputs in at least two different modes. The multi-mode circuit can be an output circuit for a logic block in an integrated circuit including an array of interconnected logic blocks, where each logic block includes a logic circuit and a multi-mode circuit. One input of each multi-mode circuit can be programmably coupled to a select output of a multi-mode circuit in an adjacent logic block. Based on the programmed mode and the tokens received, the circuit routes data between inputs and outputs of the circuit.
Abstract: A cascading input structure for logic blocks in an integrated circuit. An exemplary integrated circuit includes a plurality of substantially similar logic blocks arrayed to form a column of the logic blocks, and a self-timed vertical cascade chain. Each of the logic blocks has self-timed first and second inputs. The vertical cascade chain has a plurality of self-timed outputs, each of the self-timed outputs being coupled to a first self-timed input of a corresponding logic block in the column. In some embodiments, each logic block includes a multiply block having first and second self-timed inputs, where each output of the vertical cascade chain is coupled to the first input of the multiply block in the corresponding logic block. In some embodiments having a multiply block in the logic block, the inputs and output may not be self-timed.
Abstract: An exemplary circuit for implementing logic sharing in self-timed circuits includes a shared logic circuit, an input circuit, an output circuit, and a pipelined routing path. The shared logic circuit has first and second self-timed inputs and first and second self-timed outputs. The input circuit is coupled to output a selected one of the first or second self-timed inputs to the shared logic circuit, the selected one of the first or second inputs being determined by an arbitration circuit within the input circuit, and further to output a self-timed select signal. The output circuit is coupled to receive the first and second self-timed outputs from the shared logic circuit and to provide a selected one of the first or second outputs, the selected output being determined by the self-timed select signal. The pipelined routing path routes the self-timed enable signal from the input circuit to the output circuit.
Abstract: A bus-based logic block in a self-timed integrated circuit includes N first input multiplexers, N second input multiplexers, and N lookup tables, N being greater than one. The select inputs of all N first input multiplexers are coupled together, and the select inputs of all N second input multiplexers are coupled together. A corresponding data input of each first input multiplexer is one bit of a first self-timed N-bit bus, and a corresponding data input of each second multiplexer is one bit of a second self-timed N-bit bus. Each lookup table has first and second inputs coupled to the outputs of the first and second input multiplexers. Corresponding control inputs of all N lookup tables are coupled together. Thus, all operations are performed on one or more N-bit self-timed busses, rather than on individual data signals.
Abstract: Circuits enabling feedback paths in a self-timed integrated circuit. Each of a plurality of interconnected logic blocks includes a logic circuit having first and second outputs, and means for placing, during an initial cycle, a self-timed first data signal on the second output onto a logic block output, and for placing, during subsequent cycles, a self-timed second data signal on a selected one of the first or second outputs onto the logic block output. Initially, an output token is provided only when valid new data is received on the second output and on a select signal. Subsequently, the output token is provided only when either the first output of the logic circuit is selected, and valid new data is received on the first output and on the select signal; or the second output of the logic circuit is selected, and valid new data is received on the first and second outputs and on the select signal.
Abstract: Circuits for fanning out data in a self-timed integrated circuit. An exemplary integrated circuit includes a plurality of interconnected logic blocks, each including a logic circuit and an output circuit. The output circuit has a first data input coupled to a first output of the logic circuit, a second data input coupled to a second output of the logic circuit, and a data output coupled to a first output of the logic block. The data output reflects a value on the first data input. The output circuit is programmably coupled, in one of a plurality of operating modes, to provide an output token only when the first data input is accompanied by a first token indicating valid new data on the first data input. The output circuit is further programmably coupled to consume, when the output token is provided, both the first token and a second token accompanying the second data input.
Abstract: Systems and methods of performing co-simulation of a partitioned circuit design using multiple programmable logic devices (PLDs) coupled together to form a boundary scan chain. A host computer is coupled to the scan chain via a programming cable. Resident on the host computer are run-time co-simulation blocks corresponding to blocks from the circuit design, where each block is designated to run on one of the PLDs in the scan chain; a programming cable device driver interfacing with the programming cable; and a proxy component. The proxy component is coupled to all of the run-time co-simulation blocks and the programming cable device driver. Each co-simulation block includes a unique pattern identifier, which is also present in the associated PLD. Using this pattern identifier, data and commands targeted to a specific PLD can be extracted from the scan chain, while ignoring data and commands targeted to other PLDs in the scan chain.
September 27, 2006
Date of Patent:
June 29, 2010
Nabeel Shirazi, Jonathan B. Ballagh, Chi Bun Chan
Abstract: A programmable integrated circuit includes a plurality of interconnected logic blocks, each including a logic circuit and an output multiplexer circuit. The output multiplexer circuit includes a first multiplexer having first and second data inputs respectively coupled to first and second outputs of the logic circuit, a select input coupled to an output of another logic block, and a first data output. A second output multiplexer may also have first and second data inputs respectively coupled to the first and second outputs of the logic circuit, a select input coupled to the output of the another logic block, and a second data output. The output multiplexer circuit is programmably coupled, in one of a plurality of operating modes, to provide an output token with the first output of each logic block only when the output multiplexer circuit of the logic block receives tokens indicating valid new data on each of the first, second, and select inputs of the circuit.