Abstract: A programmable logic block provides N-bit and M-bit (e.g., (N/2)-bit) lookahead functionality for carry chains traversing the logic block, N and M being integers greater than one. An exemplary programmable logic block includes four carry multiplexers that together form a 4-bit lookahead carry chain. The 4-bit lookahead carry chain also provides a 2-bit lookahead output after the second carry multiplexer. Alternatively, the last two bits of the 4-bit lookahead carry chain can be used as a 2-bit lookahead carry chain. In one embodiment, the programmable logic block also includes four function generators associated with the four carry multiplexers. Each function generator drives a select terminal of the associated carry multiplexer. The 4-bit and 2-bit carry chains can be programmably coupled to an interconnect structure of the PLD at the carry out output terminals. In some embodiments, an initialization value can also be provided to the 4-bit and 2-bit carry chains.

Abstract: A programmable lookup table optionally provides two input signals and two output signals to an interconnect structure of a programmable integrated circuit when programmed to function as a random access memory (RAM). An integrated circuit includes an interconnect structure and a N-input lookup table (LUT) having input and output terminals coupled to the interconnect structure. The LUT can be configured to function as a single-bit wide RAM (e.g., a (2**N)×1 RAM) having N input address signals coupled to the interconnect structure and one output signal coupled to the interconnect structure, or as a multi-bit wide RAM (e.g., a (2**(N?1))×2 RAM) having fewer than N (e.g., N?1) input address signals coupled to the interconnect structure and at least two output signals coupled to the interconnect structure. Optionally, the LUT can also be configured as shift register logic, e.g., a 2**(N?1)-bit shift register or two 2**(N?2)-bit shift registers.

Abstract: Methods of testing a digital frequency synthesizer (DFS) having a programmable multiplier M and divider D. The full set of tests (wherein every value of M and D is tested) is reduced to a smaller set of tests in which each M/D ratio is tested to a specified resolution. A resolution and minimum and maximum values for M, D, and M/D are specified. An array is allocated, each M/D ratio having a corresponding location in the array, up to the specified resolution. For each MD pair meeting the specified criteria, an M/D ratio is calculated and idealized to the specified resolution, and the MD pair is stored in the corresponding array location. The result is an array of MD pairs that includes zero or one MD pair for each M/D ratio. Thus, by testing each MD pair within the array, all permissible permutations of the input clock frequency are tested.

Abstract: A programmable logic block provides programmable initialization values for carry chains traversing the logic block, without consuming user logic resources. An exemplary programmable logic block includes two or more carry multiplexers coupled together to form a carry chain for the programmable logic block. A carry initialization circuit has an output terminal coupled to a data input terminal of a first carry multiplexer in the carry chain. The carry initialization circuit is controlled by configuration memory cells of the programmable logic block to select one of a carry in signal, a power high signal, a ground signal, and (optionally) a signal from an interconnect structure of the logic block. Thus, an initialization value (e.g., power high or ground) can be provided to the carry chain without consuming other programmable resources within the logic block.

Abstract: Methods of providing error correction in configuration bitstreams for programmable logic devices (PLDs). While any error correction method can be used, in one embodiment a Hamming code is applied to instructions in the configuration bitstream, while a product code is applied to configuration data. Thus, the higher overhead required for a Hamming code applies to only a few words in the bitstream. The instructions are corrected on receipt of the word that includes the Hamming code, so the instructions are executed correctly even if a transmission error has occurred. However, configuration data can be stored in the configuration memory without correction. With a product code, the exact location of an erroneous bit is not known until the end of the transmission, when a parity word is received. At this time, the PLD can go back and correct erroneous bits in the configuration data prior to enabling the newly loaded design.

Abstract: A programmable integrated circuit (IC) provides high routing flexibility without the use of an output multiplexer structure. According to one embodiment, an IC includes programmable tiles arrayed in rows and columns. Output multiplexer structures are not included in the programmable tiles. Routing flexibility is provided in each tile by input multiplexers coupled between a general interconnect structure and the input terminals of a logic block, and by providing direct access from the logic block output terminals (e.g., lookup table outputs and memory element outputs) to both horizontal and vertical interconnect lines. In some embodiments, the logic block output signals can also drive “diagonal” interconnect lines in the general interconnect structure.

Abstract: Methods of programming an integrated circuit (IC) such as a programmable logic device to avoid localized defects present in the IC, and ICs capable of performing these methods. As part of an automated programming process, programmable resources utilized by a user design are tested, and the implemented user design is modified to avoid any defective programmable resources that are detected. The modifications can include, for example, rerouting one or more internal signals and/or substituting a fully functional programmable resource for a defective programmable resource. These methods are carried out by testing and implementation logic included in the IC. Design information such as a software device model, test program, test data, place and route program, and/or resource swapping program can be optionally included in the configuration logic or supplied in an expanded bitstream applied to the inventive IC. In some embodiments, the modified bitstream is written to an external memory device.

Abstract: Methods of estimating the susceptibility to single event upsets (SEUs) of a design implemented in an FPGA. In an FPGA, many of the configuration memory cells could change state in response to an SEU without affecting the functionality of a design implemented in the FPGA. According to the methods of the invention, the number of “care bits” (bits associated with resources actually used in the design) is determined. The number of care bits as a proportion of the total number of configuration memory cells in the FPGA determines the “SEU Probability Impact” (SEUPI) value. The “Mean Time Between Upsets” (MTBU) value is an estimate of how much time will elapse, on average, before one of the configuration memory cells in the FPGA is affected by an SEU. To obtain the “Mean Time Between Failures” for the design implemented in the FPGA, the MTBU value is divided by the SEUPI value.

Abstract: Methods of routing a design in a programmable logic device (PLD) to increase the effectiveness of applying a multi-frame write (MFW) compression technique to the resulting configuration bitstream. The methods apply placement patterns and/or routing templates to encourage the inclusion of numbers of duplicated routing paths in the routed design. The duplicated routing paths result in duplicated configuration data. Thus, a configuration bitstream implementing the routed design in the PLD includes numbers of duplicated configuration data frames, and is well-suited to benefit from MFW compression techniques.

Abstract: A configurable logic element (CLE) for a field programmable gate array (FPGA) includes “expanders”, i.e., connectors that allow fast signal communication between logic blocks. Expanders allow the configurable interconnection of a plurality of logic blocks, or portions thereof, to form a single logical entity that can implement large user circuits such as PALs, lookup tables, multiplexers, tristate buffers, and memories. One embodiment includes a configurable logic block. In a first mode, the logic block provides two N-input LUTs having N shared inputs and two separate outputs. The outputs are then combined using an expander to generate an (N+1)-input function. In a second mode, the logic block provides two N-input LUTs having M unshared inputs. An optional third mode provides a plurality of product term output signals based on the values of the N input signals.

Abstract: A memory element structure in a programmable logic device (PLD) reduces power consumption by placing the memory element in a power save mode when the memory element is unused in a user design implemented in the PLD. An exemplary structure includes a multiplexer driving a memory element. A multiplexer control circuit controls the multiplexer, and also drives a clock control circuit for the memory element. When the memory element is used by a user design implemented in the PLD, one of the data inputs is selected to drive the memory element. The controlled functions occur normally in the memory element. When the memory element is not used by the user design, none of the data inputs is selected, an input control signal is intercepted by the clock control circuit, and the controlled functions do not occur in the memory element, reducing the power consumption of the unused memory element.

Abstract: Clock multiplier circuits and methods use counters to define the positions of the output clock edges. A plurality of counters are each clocked by a count clock relatively much faster than the input clock. A first counter counts for one input clock period, and the counted value is stored. The stored value is then divided and the divided values are combined to provide counter stop values representing the numbers of counts in various fractions of the input clock period. A second counter counts from an initial value starting from a first edge of the input clock, and the count is compared in turn to the each of the counter stop values. When the value in the second counter matches one of the counter stop values, a pulse is generated on the output clock signal. Thus, the second counter generates a series of pulses at predetermined times in the input clock period.

Abstract: Methods of setting and/or resetting a lookup table (LUT) programmable to operate in shift register mode. The LUT is configured to operate as a shift register, and the final bit of the shift register is implemented using a memory element associated with the LUT. The shift register is reset (or set) by applying a reset (set) signal to the memory element, while providing a low (high) value from the memory element to a shift-in input terminal of the LUT; and shifting the low (high) value through the bits of the shift register. To perform this task, a write enable signal is provided that is independent from the reset (set) signal of the memory element and enables a shift clock signal. The shift clock signal is then repeatedly toggled to shift the low (high) value from the memory element successively through each bit of the shift register, while the value stored in the memory element is held constant by means of the independent reset (set) signal.

Abstract: In an integrated circuit including an array of substantially similar tiles, a tile includes a logic block and one or more columns of routing multiplexers driving interconnect lines that can be used to programmably interconnect the logic blocks. Each routing multiplexer in a first column drives a vertically adjacent subset of the routing multiplexers in the first and/or a second column. Optionally, each routing multiplexer also drives a vertically adjacent subset of a column of input multiplexers of a logic block. In some embodiments, the adjacent groups of routing multiplexers and input multiplexers driven by each routing multiplexer are horizontally aligned within the tile. In some embodiments, every signal coupled to drive one of the routing multiplexers in a column drives a vertically adjacent subset of the routing multiplexers. In some embodiments, each interconnect line has exit points, and every exit point drives a vertically adjacent set of the routing multiplexers.

Abstract: Efficient implementations of arithmetic functions in programmable ICs include carry chain multiplexers driven by dual-output programmable function generators. A function generator having two output signals is programmed to generate both an exclusive OR (XOR) function of first and second input signals and a second function. In some embodiments, the second function is simply the second input signal to the XOR function. In other embodiments, the second function is a different function optionally independent of the first and second input signals. The XOR function output drives the select terminal of a carry multiplexer, which selects between a carry in signal and one of the second input signal and the second function output signal to provide the carry out output signal. The sum or multiplier output value is provided by an XOR gate driven by the XOR function output and by the carry in signal, and can be optionally registered.

Abstract: A programmable logic block provides fast interconnect paths between carry multiplexer output terminals and the input terminals of function generators (e.g., lookup tables) in the same logic block. An integrated circuit includes an interconnect structure, a function generator, and a carry multiplexer having a select terminal programmably coupled to an output terminal of the function generator. An output signal from the carry multiplexer can traverse the interconnect structure to reach the input terminals of the function generator. However, a “fast connect” path is also provided that interconnects the carry multiplexer output with an input terminal of the function generator, without traversing the interconnect structure. In some embodiments, fast connect paths are also provided to input terminals of other function generators in the same logic block.

Abstract: A programmable logic block provides fast interconnect paths between memory element output terminals and the input terminals of carry multiplexers in the same logic block. An integrated circuit includes an interconnect structure, a function generator, a carry chain multiplexer coupled to an output terminal of the function generator, and a memory element programmably coupled to the output terminal of the function generator. An output signal from the memory element can traverse the interconnect structure to reach an input terminal of the carry multiplexer. However, a “fast connect” path is also provided that interconnects the memory element output with an input terminal of the carry multiplexer, without traversing the interconnect structure. In some embodiments, fast connect paths are also provided to the input terminals the function generator, and to the input terminals of other function generators and/or carry multiplexers in the same logic block.

Abstract: A programmable lookup table for an integrated circuit (IC) optionally provides two input signals and two output signals to an interconnect structure of the programmable IC when programmed to function as shift register logic. According to one embodiment, an integrated circuit includes an interconnect structure and a N-input lookup table (LUT) having input and output terminals coupled to the interconnect structure, where N is a integer. The LUT can be configured to function as a (2**(N?1))-bit shift register having a shift in input signal and one output signal coupled to the interconnect structure, or as a two (2**(N?2))-bit shift registers having two shift in input signals and two output signals coupled to the interconnect structure. In some embodiments, each bit of the shift register includes two memory cells of the LUT, a first memory cell functioning as a master latch and a second memory cell functioning as a slave latch.

Abstract: Efficient implementations of wide logic functions (e.g., priority encoders, AND gates, OR gates) in programmable ICs include carry chain multiplexers driven by dual-output programmable function generators. A function generator having two output signals is programmed to generate first and second function output signals. The first and second functions can optionally share some or all of the input signals. The first function output signal drives the select terminal of a carry multiplexer, which selects between a carry in input signal and the second function output signal to provide the carry out output signal. The wide function result is provided by the final carry multiplexer in a chain of such carry multiplexers. In an exemplary wide AND gate, the first function is an AND function, and the second function is ground. In an exemplary wide OR gate, the first function is a NOR function, and the second function is power high VDD.

Abstract: A programmable logic block reduces output delay by bypassing a final slave latch when programmed to function as a shift register. The logic block includes memory cells, a multiplexer structure, and a bypass select multiplexer (BSM). The memory cells are coupled in series to form a shift register controlled by a shift clock, each bit including two paired memory cells implementing master and slave latches. Each memory cell drives an input terminal of the multiplexer structure. The BSM drives a select terminal of the multiplexer structure and selects one signal from each pair of the memory cells. The shift clock drives one data input terminal of the BSM. When in shift register mode, the shift clock simultaneously shifts a value in each master latch to the corresponding slave latch and selects a value from one of the master latches. The output path bypasses the slave latch of the selected bit.