Abstract: Circuits for merging data streams in a self-timed programmable integrated circuit. A programmable integrated circuit includes interconnected logic blocks, each including a logic circuit and an output multiplexer circuit including an arbiter and a multiplexer. Each arbiter is coupled to receive ready signals provided with first and second outputs of the logic circuit. Each multiplexer has first and second data inputs coupled to the outputs of the logic circuit, a select input programmably coupled, in one of a plurality of operating modes, to an arbiter output, and a data output coupled to an output of the logic block. The output multiplexer circuit provides an output token only when a first token indicates valid new data on the arbiter output and a second token indicates valid new data on one of the data inputs, and stores a third token received on the other data input until the other data input is selected by the multiplexer.

Abstract: A multi-mode circuit for a self-timed integrated circuit is provided. The multi-mode circuit is programmable to operate in two or more modes, and is coupled to require, in each mode, receipt of a token on at least one of first, second, or third inputs before providing an output token. The multi-mode circuit is further coupled to require tokens on different inputs in at least two different modes. The multi-mode circuit can be an output circuit for a logic block in an integrated circuit including an array of interconnected logic blocks, where each logic block includes a logic circuit and a multi-mode circuit. One input of each multi-mode circuit can be programmably coupled to a select output of a multi-mode circuit in an adjacent logic block. Based on the programmed mode and the tokens received, the circuit routes data between inputs and outputs of the circuit.

Abstract: A bus-based logic block in a self-timed integrated circuit includes N first input multiplexers, N second input multiplexers, and N lookup tables, N being greater than one. The select inputs of all N first input multiplexers are coupled together, and the select inputs of all N second input multiplexers are coupled together. A corresponding data input of each first input multiplexer is one bit of a first self-timed N-bit bus, and a corresponding data input of each second multiplexer is one bit of a second self-timed N-bit bus. Each lookup table has first and second inputs coupled to the outputs of the first and second input multiplexers. Corresponding control inputs of all N lookup tables are coupled together. Thus, all operations are performed on one or more N-bit self-timed busses, rather than on individual data signals.

Abstract: Circuits for fanning out data in a self-timed integrated circuit. An exemplary integrated circuit includes a plurality of interconnected logic blocks, each including a logic circuit and an output circuit. The output circuit has a first data input coupled to a first output of the logic circuit, a second data input coupled to a second output of the logic circuit, and a data output coupled to a first output of the logic block. The data output reflects a value on the first data input. The output circuit is programmably coupled, in one of a plurality of operating modes, to provide an output token only when the first data input is accompanied by a first token indicating valid new data on the first data input. The output circuit is further programmably coupled to consume, when the output token is provided, both the first token and a second token accompanying the second data input.

Abstract: Circuits for implementing gating logic in a self-timed integrated circuit. An integrated circuit includes a plurality of interconnected logic blocks, each including a logic circuit and an output circuit. Each output circuit has a data input coupled to an output of the logic circuit, a gating input, and a data output coupled to an output of the logic block. The output circuit is coupled to place a value on the data input onto the data output when the gating input has a first value and the output circuit receives tokens indicating valid new data on both the data input and the gating input of the output circuit. The output circuit is coupled to leave the data output unchanged when the gating input has a second value and the output circuit receives a token indicating valid new data on both the data and gating inputs of the output circuit.

Abstract: Methods of initializing an integrated circuit (IC) in which the routing structures have data lines and handshake circuitry are provided. A node of each of the data lines is driven to a predetermined value, and the handshake circuit is disabled by disabling an acknowledge path within the handshake circuitry, e.g., by forcing all acknowledge signals in the acknowledge path to signal an acknowledgement of received data. The disablement causes the predetermined value to propagate throughout the data lines. The handshake circuitry is then enabled by enabling the acknowledge path, which releases the data lines to assume values determined by operation of the IC. When the IC is a programmable IC, configuration values may be programmed into the IC after disabling the acknowledge path and before enabling the handshake circuitry. When the handshake circuitry is enabled, the data lines assume initial values determined by the programmed configuration values.

Abstract: An exemplary circuit for implementing conditional statements in self-timed logic circuits includes first and second logic circuits, an input circuit, an output circuit, and a pipelined routing path. The first and second logic circuits each have a self-timed input and a self-timed output. The input circuit is coupled to provide a self-timed input signal to the self-timed input of a selected one of the first or second logic circuits based on the value of a control signal, and is further coupled to output a self-timed select signal. The output circuit is coupled to receive the self-timed output from the first logic circuit and the self-timed output from the second logic circuit, and to output a selected one of the self-timed outputs based on a value of the self-timed select signal. The pipelined routing path routes the self-timed select signal from the input circuit to the output circuit.

Abstract: Methods of estimating delays between pins on a tile-based programmable logic device (PLD), by identifying repeat patterns and exploiting these patterns to provide accurate delay estimates. A computer-implemented method can include selecting a sample area in a tile-based PLD and constructing a delay table corresponding to the sample area. Each entry in the delay table includes a base delay value and a description of the fastest available route from a source pin in a source tile to a load pin in the sample area. To estimate a net delay, the base delay value and the description of the route are read from the delay table for specified source and load pins. One or more delay variants (e.g., pin delays and/or crossing penalties) are calculated based on the description of the route. The calculated delay variants are added to the base delay value to obtain an adjusted delay value, which is output.

Abstract: Functional testing of an integrated circuit (IC) is a part from a more comprehensive and thorough testing. An IC including an embedded select circuit module coupled to receive numerous input signals. The IC may also include control circuit coupled to receive input control signals, where at least one input control signal of the input control signals is a mode signal. Asserting the mode signal may operate the select circuit module in a test mode.

Abstract: Circuits and methods of suppressing signal glitches in an integrated circuit (IC). A glitch on a signal entering a clock buffer, for example, is prevented from propagating through the clock buffer. In some embodiments, a latch is added to an input clock path that detects a transition on the input signal, and then ignores any subsequent transitions for a time delta that is determined by a delay circuit. In some embodiments, a multiplexer circuit is used to select between the input clock signal and the output clock signal, with changes on the input clock signal not being passed through the multiplexer circuit unless the time delta has already elapsed. In some embodiments, the delay is programmable, pin-selectable, or self-adapting.

Abstract: Integrated circuits (ICs) having bus-based programmable interconnect structures are provided. An IC includes substantially similar logic blocks and a programmable interconnect structure programmably interconnecting the logic blocks. The programmable interconnect structure includes bus structures and programmable switching structures programmably interconnecting the bus structures. Each bus structure includes N data lines, where N is an integer greater than one, and N commonly controlled storage elements (e.g., latches) for storing data on the N data lines. In some embodiments, at least one of the bus structures includes handshake logic, including a C-element coupled to drive a ready line, to receive an acknowledge line, and to provide a control signal to each of the N storage elements in the bus structure.

Abstract: An output circuit providing an adjustable output amplitude and common-mode voltage is described. The output circuit includes at least one driver circuit and a common-mode feedback circuit including a first replica circuit of the at least one driver circuit. The common-mode feedback circuit is coupled to receive a first bias and provide an output coupled to the at least one driver circuit. The output circuit may also include a current circuit having a configurable resistor and a second replica circuit of the at least one driver circuit. The current circuit may be coupled to receive a second bias and to provide an output coupled to the at least one driver circuit and the common-mode feedback circuit.

Abstract: Structures and methods of efficiently implementing power management in integrated circuits (ICs). An IC includes columns of logic blocks and columns of power management blocks (PMBs). The columns of PMBs and logic blocks are placed alternately across the IC, with each PMB being coupled to a logic block in an adjacent column, and the logic blocks are coupled to each other across the columns of PMBs. The PMBs can be implemented, for example, using power gates coupled between a global power rail (either ground or power high) and a local power rail specific to the associated logic block. A PMB can be selected from a library of interchangeable PMBs based on power and performance requirements of a target application. Because the PMB is designed as a separate block, any of the interchangeable PMBs in the library can readily be included in the IC.

Abstract: Methods of securing a programmable logic device (PLD) when an intrusion attempt is detected, e.g., methods of erasing sensitive data from the PLD or disabling configuration of the PLD in response to an attack. For example, when an attempt is made to configure the PLD with an unauthorized bitstream, a decryption key stored on the PLD can be erased, or decryption logic in the PLD can be otherwise disabled. The criteria for assuming that an attack is in progress can include, for example, the lack of a cyclic redundancy check (CRC) value included with a configuration bitstream, an attempt to operate the PLD outside normal operating ranges, receipt of an incorrect CRC value, or receipt of a predetermined number of bitstreams including incorrect CRC values. In some embodiments, an error correction procedure is performed on the bitstream, thereby preventing most transmission errors from being incorrectly interpreted as an attack.

Abstract: Integrated circuits (ICs) having novel handshake logic are provided. An IC includes a ready multiplexer, an acknowledge demultiplexer, a C-element coupled to the ready multiplexer and the acknowledge demultiplexer, a logic gate, and a storage element (e.g., a latch). The logic gate has a first input coupled to a control output of the C-element, and a second input. The storage element includes a data multiplexer and a latch. The data multiplexer has M data inputs coupled to data inputs of the storage element, a select input coupled to the output of the logic gate, and a data output, M being an integer greater than one. The latch has a data input coupled to the data output of the first data multiplexer and an output coupled to an output of the storage element. The logic gate can be a logical AND gate with the second input coupled to a memory cell.

Abstract: Methods of detecting unwanted logic in an integrated circuit (IC) design. Any unwanted logic added to a design (e.g., to monitor or interfere with operation of the design) will draw power from one or more power supplies on the IC. Hence, by monitoring power drawn from various portions of a circuit design implemented in an IC, the unwanted logic can be detected and reported to the user. One way of monitoring power draw is by the use of oscillator circuits. If power goes down locally (e.g., due to the operation of unwanted logic), the frequency of an oscillator circuit in that vicinity will be reduced relative to the frequencies of other oscillator circuits in the design, and/or relative to an expected value. When a variation in the relative power consumption is detected, unwanted logic can be inferred and an error signal is output.

Abstract: Methods of generating a PLD design implementation according to a design architecture tailored to specified requirements. A hardware description language (HDL) description for the PLD design includes at least one parameter value for the PLD design that will affect the preferred implementation of the design. This parameter value is passed to a high-level language (HLL) function, which is used to determine a tailored design architecture in accordance with the specified needs of the target application. The HLL function returns data specifying the tailored design architecture. This data is used in generating an implementation of the PLD design that follows the constraints imposed by the tailored design architecture. The result can be, for example, a logic gate representation of the PLD design, a netlist of the design, or a bitstream implementing the design in a target PLD.

Abstract: An input/output (I/O) structure includes a delay element usable for the input path, the output path, or both input and output paths in a user design. In a first mode, the delay element is included in the input path. In a second mode, the delay element is included in the output path. In a third mode, the I/O structure includes the delay in both outgoing signal paths and incoming signal paths, e.g., by utilizing an output tristate signal to control the direction of the delay line. When the output buffer is driving, the delay is inserted in the output path. When the output buffer is tristated, the delay is inserted in the input path. Thus, a single delay element is dynamically shared by both input and output signals that use the same I/O pad. In an optional fourth mode, the delay element is bypassed by both input and output signals.

Abstract: Methods of implementing state machines using embedded processors. The designer specifies the logical footprint of the state machine in a formalism that can be transformed into hardware. This approach decouples the designer from the design, so that a state machine can be moved between embedded processors (e.g., between a hard processor and a soft processor), without any modifications to the code. One or more source-to-source transformations can be performed to improve the run-time performance of the state machine. These transformations can include the insertion of one or more jump addresses directly into the code, bypassing the standard lookup table approach for memory addressing, and consequently speeding up the execution of the code. The jump addresses can include, for example, a jump address for the start of each state machine, and/or a jump address for each state within the state machines.

Abstract: Structures and methods of avoiding hold time violations in a design implemented in a PLD. In a programmable device, the delay of a signal path varies, e.g., depending on the separation between the source and destination of the signal. An optional delay element is provided between a programmable interconnect structure and a destination logic element having a clock skew relative to the source. The optional delay element is programmed by the implementation software to introduce a delay on the signal path when necessary to meet the hold time requirements for the destination logic element. The optional delay is designed to be large enough to overcome hold-time violations even for the largest possible clock skew and the smallest possible signal delay. When no hold time violation occurs, the optional delay element is configured to bypass the additional delay, to avoid imposing a large setup requirement on the signal.