Abstract: Optical characteristic measuring systems and methods such as for determining the color or other optical characteristics of teeth are disclosed. Perimeter receiver fiber optics are spaced apart from a source fiber optic and receive light from the surface of the object/tooth being measured. Light from the perimeter fiber optics pass to a variety of filters. The system utilizes the perimeter receiver fiber optics to determine information regarding the height and angle of the probe with respect to the object/tooth being measured. Under processor control, the optical characteristics measurement may be made at a predetermined height and angle. Various color spectral photometer arrangements are disclosed. Translucency, fluorescence, gloss and/or surface texture data also may be obtained. Audio feedback may be provided to guide operator use of the system. The probe may have a removable or shielded tip for contamination prevention. A method of producing dental prostheses based on measured data also is disclosed.

Abstract: To obtain a correct vector address even if an interrupt occurs during erasing or programming of the data in a built-in ROM 18 by moving a part of a built-in RAM13 to a vector address area by a bus controller 27. Thereby, a microcomputer is prevented from running away and the safety of a system is improved at the time of on-board programming of the built-in ROM 18.

Abstract: A method for removing etch residue material in which the removing process is simple, and the metal is prevented from being corroded or damaged. The method for removing etch residue materials and photoresist after carrying out a dry etching includes the steps of preparing a dry chemical by using one or more gas compounds, and removing the etch residue materials by raising the dry chemical above a critical point, wherein the dry chemical comprises carbon dioxide gas and one or more gases selected from a group consisting of DMSO (dimethyl sulfoxide), DMFA (dimethyl formamide), and THF (phentydrone).

Abstract: Color measuring systems and methods such as for determining the color or other characteristics of teeth are disclosed. Perimeter receiver fiber optics are spaced apart from a central source fiber optic and receive light reflected from the surface of the object/tooth being measured. Light from the perimeter fiber optics pass to a variety of filters. The system utilizes the perimeter receiver fiber optics to determine information regarding the height and angle of the probe with respect to the object/tooth being measured. Under processor control, the color measurement may be made at a predetermined height and angle. Various color spectral photometer arrangements are disclosed. Translucency, fluorescence and/or surface texture data also may be obtained. Audio feedback may be provided to guide operator use of the system. The probe may have a removable or shielded tip for contamination prevention. A method of producing dental prostheses based on measured data also is disclosed.

Abstract: A complementary clock generator and a method for generating complementary clocks are disclosed. A complementary clock generator according to the present invention includes a first inverter, a first transmitting switch and a second transmitting switch. The first inverter outputs inverted clock signals by inverting input clock signals. The first transmitting switch has an input terminal, an output terminal, a first control input terminal and a second control input terminal, and connects the input terminal to the output terminal when the input clock signal reaches the first control input terminal and the inverted clock signal from the first inverter reaches the second control input terminal.

Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

Abstract: An electronic circuit board with one or more semiconductor chips installed thereon, and a manufacturing method therefor, are disclosed. The circuit board with semiconductor chips installed thereon includes: one or more semiconductor chips; an insulated circuit board having wire bonding pads for connection to the bonding pads of the semiconductor chips; a plurality of wires connected between the bonding pads of the semiconductor chips and the wire bonding pads of the circuit board; and a plurality of protecting covers for insulating the wires and the semiconductor chips. The circuit board includes an opening smaller than the semiconductor chips, and wire bonding pads formed around the opening. The semiconductor chip includes bonding pads which are formed on the central portion of the surface of the semiconductor chip. The protective cover covers the chip and the wires.

Abstract: Color measuring systems and methods such as for determining the color or other characteristics of teeth are disclosed. Perimeter receiver fiber optics are spaced apart from a central source fiber optic and receive light reflected from the surface of the object/tooth being measured. Light from the perimeter fiber optics pass to a variety of filters. The system utilizes the perimeter receiver fiber optics to determine information regarding the height and angle of the probe with respect to the object/tooth being measured. Under processor control, the color measurement may be made at a predetermined height and angle. Various color spectral photometer arrangements are disclosed. Translucency, fluorescence and/or surface texture data also may be obtained. Audio feedback may be provided to guide operator use of the system. The probe may have a removable or shielded tip for contamination prevention. A method of producing dental prostheses based on measured data also is disclosed.

Abstract: A microprocessor comprising a bus state controller and for use in a personal computer or the like. The bus state controller includes control registers such as wait controllers, and in parallel controls the interfaces of various semiconductor memories (ROM, burst ROM, SRAM, PSRAM, DRAM and synchronous RAM) and PC cards (memory and I/O cards). Also included in the bus state controller is a control register for controlling the time to set up PC card start signals where a synchronous DRAM(s) is configured. The address space of an external bus of the microprocessor is divided into a predetermined number of areas to which the semiconductor memories and PC cards are fixedly assigned. The microprocessor further comprises a memory management unit for converting an internally prepared logical address to a physical address.

Abstract: A semiconductor package is provided. A semiconductor chip including bonding pads has a plurality of leads disposed on and attached to the upper surface of the semiconductor chip. The leads include bonding tips that are electrically connected to the bonding pads by bonding wires. A molding compound encapsulates the chip and portions of the leads. Upper portions of the leads extend from the molding compound. The exposed upper portions of the leads may be connected to a circuit board. Heat dissipation from the semiconductor chip is facilitated with the disclosed package.

Abstract: An improved p+ polysilicon gated PMOSFET having a channel on the surface of a silicon substrate and improved short channel behavior is disclosed. A simplified process allows making a p+ doped gate and source/drain regions at the same time, the transistor particularly having a stable threshold voltage. The disclosed method provides the steps of: (A) forming an active region and an insulation region on an n-type semiconductor substrate; growing a gate insulating layer on the silicon substrate; depositing a polysilicon layer on the gate insulating layer; annealing the polysilicon layer in the presence of NH.sub.3 or other nitrogen-containing gas; (C) forming a gate line by patterning and etching the polysilicon layer; and (D) implanting BF.sub.2 ions into the semiconductor substrate.

Abstract: The present invention provides a process for forming an MOS semiconductor device having an LDD structure, which includes a forming a gate electrode by first etching a conductive layer to a certain depth by an RIE process and by second etching the conductive layer by an isotropic plasma etching process. In forming the source/drain of the device, an n.sup.+ source/drain and an n.sup.- source/drain are formed in a sequential manner. The gate line first is formed with its width over-sized compared with its channel length, and finally is formed to its final size.

Abstract: An improved high resolution method and apparatus are described for sensing and determining the spatial coordinates of a movable object with respect to a energized conductive surface. The coordinates of the object are precisely measured with respect to a two-dimensional coordinate system independent of the third orthogonal dimension, thereby avoiding significant measurement errors due to variations of the object position in the third orthogonal dimension. The system also ascertains the coordinate position of the object in this third dimension, which can then be utilized as an independent control variable in the system. Further, the system can accommodate a number of energized conductive surfaces over which the object may be positioned and can determine the spatial coordinates of the object with respect to any such surface.

Abstract: In an on-screen display (OSD) circuit and position detector, the OSD circuit includes a menu OSD circuit for outputting video signals Rm, Gm and Bm and switch signal Ym, a pointer OSD circuit for selecting displayed menu items and for outputting video signals Rp, Gp and Bp and switch signal Yp, and a pointer or menu selecting circuit for receiving the video signals of the menu OSD circuit, Rm, Gm and Bm and switch signal Ym as inputs, and receiving the video signals of the pointer OSD circuit, Rp, Gp and Bp and switch signal Yp as inputs to then first select the output of the pointer OSD circuit, and then to selectively output the output of the menu OSD circuit if there is no output from the pointer OSD circuit.

Abstract: A spare decoder circuit generates a redundancy signal which accesses a redundancy cell on behalf of a failed cell when an input address for repairing the failed cell accesses the failed cell in a memory device having a redundancy cell. The spare decoder circuit includes: a first programming part which includes a first signal line for generating a redundancy signal; first enabling means for providing a constant electric potential to the first signal line; and first programming cells which are connected to an address line and control an electric potential of the first signal line; and a second programming part which includes: a second signal line for generating a redundancy signal; second enabling means for providing a constant electric potential to the second signal line; and second programming cells which are connected to an address line, and controls an electric potential of the second signal line.

Abstract: A MOSFET comprising a gate oxide layer on a silicon substrate, a polysilicon gate formed on the gate oxide layer, the length of which gradually widens going from bottom to top, a side gate oxide layer formed by an oxidation process surrounding the polysilicon gate, the side gate oxide layer also gradually widening from bottom to top, a source/drain region beside the gate oxide layer, a connection element having a stacked structure of a polysilicon and/or polycide layer on the field oxide, a doped polysilicon side wall beside the side gate oxide layer and making electric connection between the source/drain region and the connection element.

Abstract: An improved contact hole plug and method are disclosed, the plug connecting a first conductive layer to a second conductive layer which is insulated from the first conductive layer. The contact hole plug may be formed using the steps of: (1) forming a first conductive layer consisting of a multi-layer metal (2) forming an inter-layer insulating film, and a contact hole therein; and (3) carrying out a rapid heat treatment which causes an alloy reaction in the multi-layer metal, and the resulting alloy expands to form a plug in the contact hole. The rapid heat treatment may be accomplished with a heat treatment furnace or a rapid thermal annealing (RTA) process at a temperature of 300.degree.-600.degree. C. for about 30 seconds (RTA) or 30 minutes (heating furnace).

Abstract: A semiconductor memory device including a semiconductor substrate having a trench; a dielectric film formed on the substrate; a storage node electrode formed on the dielectric film; a first insulating film formed on the storage node electrode corresponding to the trench; a gate electrode formed on the first insulating film; a second insulating film formed on the gate electrode; a gate insulating film formed on at least one the side of gate electrode; a semiconductor layer formed on the at least one side of the first and second insulating films; and impurity regions formed in the semiconductor layer at the sides of the first and second insulating films.

Abstract: A .DELTA..SIGMA. analog-to-digital converter having a built-in variable gain end is disclosed including a .DELTA..SIGMA. analog-to-digital converter portion, the converter portion having an amplifier for amplifying and outputting an input signal, a charging device for accumulating a signal voltage, a plurality of switches coupling the input signal to the charging device and coupling the voltage accumulated in the charging device to the amplifier, and a comparator for producing a HIGH output if the output of the amplifier becomes above a predetermined level, and producing a LOW output if the output of the amplifier becomes below the predetermined level, and an AGC controller both ends of which are coupled to a reference voltage, the controller generating a voltage reduced into 1/N of the reference voltage through switches at respective nodes of a plurality of resistors.

Abstract: A semiconductor package having outer leads which are not protruded from the package but only exposed to outside. The semiconductor package comprises a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface, a lead frame including leads connected to bond pads for input/output of the bond pads respectively and bus bars connected to power supplying pads of the bond pads, insulation adhesives for attaching inner leads of the leads and inner leads of the bus bars to a bottom surface of the semiconductor chip formed with the bond pads, metal wires for electrically connecting the inner leads of the leads and the inner leads of the bus bars to the bond pads respectively, and a molding compound enveloping the semiconductor chip assembly with outer leads of the lead frame exposed to outside. The adhesive tapes are removed after a molding procedure.