Semiconductor package for a semiconductor chip having centrally located bottom bond pads
A semiconductor package having outer leads which are not protruded from the package but only exposed to outside. The semiconductor package comprises a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface, a lead frame including leads connected to bond pads for input/output of the bond pads respectively and bus bars connected to power supplying pads of the bond pads, insulation adhesives for attaching inner leads of the leads and inner leads of the bus bars to a bottom surface of the semiconductor chip formed with the bond pads, metal wires for electrically connecting the inner leads of the leads and the inner leads of the bus bars to the bond pads respectively, and a molding compound enveloping the semiconductor chip assembly with outer leads of the lead frame exposed to outside. The adhesive tapes are removed after a molding procedure.
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Claims
3. A semiconductor package according to claim 1, wherein said adhesive is an insulating film.
4. A semiconductor package according to claim 1, wherein said adhesive is insulating paste.
5. A semiconductor package according to claim 1, wherein said metal wires are gold wires.
6. A semiconductor package according to claim 1, wherein said metal wires are aluminum wires..Iadd.7. A semiconductor package, comprising:
- a semiconductor chip;
- a plurality of contoured leads attached to the semiconductor chip with an insulator and having at least a first portion and a second portion, wherein the contoured leads extend away from a bottom surface of the semiconductor package to provide for wire bonding of the leads to the semiconductor chip;
- connectors electrically connecting the chip to the first portion of the leads; and
- a molding compound formed completely around the chip and also formed around the connectors and at least the first portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points, wherein the exposed second portion of the leads is positioned on and flush with the bottom surface of the semiconductor package..Iaddend..Iadd.8. The semiconductor package of claim 7, wherein the leads are elongated..Iaddend..Iadd.9. The semiconductor package of claim 7, wherein the semiconductor chip has a length, wherein the leads extend along the length of the semiconductor chip..Iaddend..Iadd.10. The semiconductor package of claim 7, wherein the semiconductor chip has a major surface on which are formed circuit elements, wherein the leads are attached to the major surface by an insulating adhesive..Iaddend..Iadd.11. The semiconductor package of claim 10, wherein the leads are attached at a central portion of the major surface..Iaddend..Iadd.12. The semiconductor package of claim 10, wherein the insulating adhesive comprises an
insulating film..Iaddend..Iadd.13. The semiconductor package of claim 10, wherein the insulating adhesive comprises an insulating paste..Iaddend..Iadd.14. The semiconductor package of claim 7, wherein at least one of the leads comprises a power supply bus bar..Iaddend..Iadd.15. The semiconductor package of claim 14, wherein the power supply bus bar is attached to a central portion of the semiconductor chip..Iaddend..Iadd.16. The semiconductor package of claim 7, wherein the connectors comprise bonding wires..Iaddend..Iadd.17. The semiconductor package of claim 7, wherein the electrical connection points provide electrical connections for connecting the semiconductor package to a printed circuit board..Iaddend..Iadd.18. The semiconductor package of claim 7, wherein the exposed second portions of the leads do not extend beyond the bottom surface of the semiconductor package..Iaddend..Iadd.19. A semiconductor package, comprising:
- a semiconductor chip;
- a plurality of contoured leads attached to the semiconductor chip with an insulator and having at least a first portion and a second portion;
- connectors electrically connecting the chip to the first portion of the leads; and
- a molding compound formed completely around the chip and also formed around the connectors and at least the first portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points, wherein the exposed second portion of the leads is positioned on and flush with a bottom surface of the semiconductor package, and wherein the exposed second portion of the leads comprise less than a majority portion of the area of the bottom surface..Iaddend..Iadd.20. The semiconductor package of claim 19, wherein the leads are contoured to extend away from the bottom surface of the semiconductor package..Iaddend..Iadd.21. The semiconductor package of claim 19, wherein the leads are elongated and contoured to extend away from the bottom surface of the semiconductor package..Iaddend..Iadd.22. The semiconductor package of claim 19, wherein the semiconductor chip has a length, wherein the leads extend along the length of the semiconductor
chip..Iaddend..Iadd.3. The semiconductor package of claim 19, wherein the semiconductor device comprises a memory device..Iaddend..Iadd.24. The semiconductor package of claim 19, wherein the semiconductor chip has a major surface on which are formed circuit elements, wherein the leads are attached to the major surface by an insulating adhesive..Iaddend..Iadd.25. The semiconductor package of claim 24, wherein the leads are attached at a central portion of the major surface..Iaddend..Iadd.26. The semiconductor package of claim 24, wherein the insulating adhesive comprises an insulating film..Iaddend..Iadd.27. The semiconductor package of claim 24, wherein the insulating adhesive comprises an insulating paste..Iaddend..Iadd.28. The semiconductor package of claim 19, wherein at least one of the leads comprises a power supply bus bar..Iaddend..Iadd.29. The semiconductor package of claim 28, wherein the power supply bus bar is attached to a central portion of the semiconductor chip..Iaddend..Iadd.30. The semiconductor package of claim 19, wherein the connectors comprise bonding wires..Iaddend..Iadd.31. The semiconductor package of claim 19, wherein the electrical connection points provide electrical connections for connecting the semiconductor package to a printed circuit board..Iaddend..Iadd.32. The semiconductor package of claim 19, wherein the exposed second portions of the leads do not extend beyond the bottom surface of the semiconductor package..Iaddend..Iadd.33. A semiconductor package, comprising:
- a semiconductor chip, wherein the semiconductor chip comprises a length;
- a plurality of contoured leads attached to the semiconductor chip with an insulator and having at least a first portion and a second portion, wherein the leads extend along the length of the semiconductor chip, and wherein the leads do not extend beyond the length of the semiconductor chip;
- connectors electrically connecting the chip to the first portion of the leads;
- a molding compound formed completely around the chip and also formed around the connectors and at least the first portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points, wherein the exposed second portion of the leads is flush with a
surface of the semiconductor package..Iaddend..Iadd.34. The semiconductor package of claim 33, wherein the semiconductor device comprises a memory device..Iaddend..Iadd.35. The semiconductor package of claim 33, wherein the semiconductor chip has a major surface on which are formed circuit elements, wherein the leads are attached to the major surface by an insulating adhesive..Iaddend..Iadd.36. The semiconductor package of claim 35, wherein the leads are attached at a central portion of the major surface..Iaddend..Iadd.37. The semiconductor package of claim 35, wherein the insulating adhesive comprises an insulating film..Iaddend..Iadd.38. The semiconductor package of claim 35, wherein the insulating adhesive comprises an insulating paste..Iaddend..Iadd.39. The semiconductor package of claim 33, wherein at least one of the leads comprises a power supply bus bar..Iaddend..Iadd.40. The semiconductor package of claim 39, wherein the power supply bus bar is attached to a central portion of the semiconductor chip..Iaddend..Iadd.41. The semiconductor package of claim 33, wherein the connectors comprise bonding wires..Iaddend..Iadd.42. The semiconductor package of claim 33, wherein the electrical connection points provide electrical connections for connecting the semiconductor package to a printed circuit board..Iaddend..Iadd.43. The semiconductor package of claim 33, wherein the exposed second portions of the leads are positioned on a bottom surface of the semiconductor package, wherein the exposed second portions of the leads do not extend beyond the bottom surface of the semiconductor package..Iaddend..Iadd.44. A semiconductor package, comprising:
- a semiconductor chip, wherein the semiconductor chip has a major surface on which are formed circuit elements;
- a plurality of contoured leads attached to the semiconductor chip with an insulator and having at least a first portion and a second portion, wherein the leads are attached to the major surface by an insulating adhesive;
- connectors electrically connecting the chip to the first portion of the leads;
- a molding compound formed completely around the chip and also formed around the connectors and at least the first portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points, wherein the exposed second portion of the leads is flush with a
surface of the semiconductor package..Iaddend..Iadd.45. The semiconductor package of claim 44, wherein the semiconductor chip has a length, wherein the leads extend along the length of the semiconductor chip..Iaddend..Iadd.46. The semiconductor package of claim 44, wherein the semiconductor device comprises a memory device..Iaddend..Iadd.47. The semiconductor package of claim 44, wherein the leads are attached at a central portion of the major surface..Iaddend..Iadd.48. The semiconductor package of claim 44, wherein the insulating adhesive comprises an insulating film..Iaddend..Iadd.49. The semiconductor package of claim 44, wherein the insulating adhesive comprises an insulating paste..Iaddend..Iadd.50. The semiconductor package of claim 44, wherein at least one of the leads comprises a power supply bus bar..Iaddend..Iadd.51. The semiconductor package of claim 50, wherein the power supply bus bar is attached to a central portion of the semiconductor chip..Iaddend..Iadd.52. The semiconductor package of claim 44, wherein the connectors comprise bonding wires..Iaddend..Iadd.53. The semiconductor package of claim 44, wherein the electrical connection points provide electrical connections for connecting the semiconductor package to a printed circuit board..Iaddend..Iadd.54. The semiconductor package of claim 44, wherein the exposed second portions of the leads are positioned on a bottom surface of the semiconductor package, wherein the exposed second portions of the leads do not extend beyond the bottom surface of the semiconductor
package..Iaddend..Iadd.55. A semiconductor package, comprising:
- a semiconductor chip;
- a plurality of contoured leads attached to the semiconductor chip with an insulator and having at least a first portion and a second portion, wherein at least one of the leads comprises a power supply bus bar;
- connectors electrically connecting the chip to the first portion of the leads;
- a molding compound formed completely around the chip and also formed around the connectors and at least the first portion of the leads, wherein the second portion of the leads is exposed to provide electrical connection points, wherein the exposed second portion of the leads is flush with a surface of the semiconductor package..Iaddend..Iadd.56. The semiconductor package of claim 55, wherein the semiconductor device comprises a memory device..Iaddend..Iadd.57. The semiconductor package of claim 55, wherein the semiconductor chip has a major surface on which are formed circuit elements, wherein the leads are attached to the major surface by an insulating adhesive..Iaddend..Iadd.58. The semiconductor package of claim 57, wherein the leads are attached at a central portion of the major surface..Iaddend..Iadd.59. The semiconductor package of claim 57, wherein the insulating adhesive comprises an insulating film..Iaddend..Iadd.60. The semiconductor package of claim 57, wherein the insulating adhesive comprises an insulating paste..Iaddend..Iadd.61. The semiconductor package of claim 55, wherein the power supply bus bar is attached to a central portion of the semiconductor chip..Iaddend..Iadd.62. The semiconductor package of claim 55, wherein the connectors comprise bonding wires..Iaddend..Iadd.63. The semiconductor package of claim 55, wherein the electrical connection points provide electrical connections for connecting the semiconductor package to a printed circuit board..Iaddend..Iadd.64. The semiconductor package of claim 55, wherein the exposed second portions of the leads are positioned on a bottom surface of the semiconductor package, wherein the exposed second portions of the leads do not extend beyond the bottom surface of the semiconductor package..Iaddend.
3940786 | February 24, 1976 | Scheingold et al. |
4532419 | July 30, 1985 | Takeda |
4539472 | September 3, 1985 | Poetker et al. |
4937656 | June 26, 1990 | Kohara |
5107325 | April 21, 1992 | Nakayoshi |
5122860 | June 16, 1992 | Kikuchi et al. |
5157480 | October 20, 1992 | McShane et al. |
5166866 | November 24, 1992 | Kim et al. |
5172214 | December 15, 1992 | Casto |
5229846 | July 20, 1993 | Kozuka |
5235207 | August 10, 1993 | Ohi et al. |
5436500 | July 25, 1995 | Park et al. |
5583375 | December 10, 1996 | Tsubosaki et al. |
5693573 | December 2, 1997 | Choi |
0198194 | October 1986 | EPX |
0465143 | January 1992 | EPX |
0501830 | September 1992 | EPX |
3911711 | October 1990 | DEX |
51-16701 | February 1976 | JPX |
57-176751 | October 1982 | JPX |
58-11198 | January 1983 | JPX |
60-15786 | January 1985 | JPX |
60-68488 | April 1985 | JPX |
60-183745 | September 1985 | JPX |
60-257159 | December 1985 | JPX |
61-222715 | October 1986 | JPX |
62-2560 | January 1987 | JPX |
62-76540 A | April 1987 | JPX |
62-134944 | June 1987 | JPX |
62-154769 | July 1987 | JPX |
62-249464 | October 1987 | JPX |
2298146 | December 1987 | JPX |
62-298146 A | December 1987 | JPX |
63-67763 A | March 1988 | JPX |
3151058 | June 1988 | JPX |
63-151058 | June 1988 | JPX |
63-258050 | October 1988 | JPX |
63-296252 A | December 1988 | JPX |
263142 | March 1990 | JPX |
2-47061 | March 1990 | JPX |
2-246125 | October 1990 | JPX |
3-131059 A | June 1991 | JPX |
3131059 | June 1991 | JPX |
5-166964 A | July 1993 | JPX |
6-132453 A | May 1994 | JPX |
6-236956 A | August 1994 | JPX |
- Goodenough, Frank: "Mixing Gold and Aluminum Bond Wires on Power Ics Cuts Cost and Ups Reliability"; 1990; p. 34; In: Electronic Design, 11, H..19. Bregmann, Mark F. and Kovac, Carolin A; "Plastic for VLSI-Based Computers"; Jun. 1968, H.6, S.75-80; In: Solid State Technology.
Type: Grant
Filed: Nov 8, 1996
Date of Patent: Feb 16, 1999
Assignee: LG Semicon, Ltd. (Chungcheongbuk-Do)
Inventor: Gi Bon Cha (Cheong-ju)
Primary Examiner: Leo P. Picard
Assistant Examiner: John B. Vigushin
Law Firm: Loudermilk & Associates
Application Number: 8/748,460
International Classification: H01L 2348;