Abstract: A power gating circuit configured to couple with a memory array having an internal voltage, wherein the power gating circuit includes circuitry having an output signal that raises the internal voltage of the memory array if the internal voltage is lower than a first threshold voltage, and lowers the internal voltage if the internal voltage is higher than a second threshold voltage, thereby retaining the internal voltage between the first threshold voltage and the second threshold voltage.

Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to an interconnection structure for N/P metal gates. An exemplary structure for an interconnection structure comprises a first gate electrode having a first portion of a first work-function metal layer under a first portion of a signal metal layer; and a second gate electrode having a second portion of the first work-function metal layer interposed between a second work-function metal layer and a second portion of the signal metal layer, wherein the second portion of the signal metal layer is over the second portion of the first work-function metal layer, wherein the second portion of the signal metal layer and the first portion of the signal metal layer are continuous, and wherein a maximum thickness of the second portion of the signal metal layer is less than a maximum thickness of the first portion of the signal metal layer.

Abstract: An integrated gate driver circuit receives a plurality of clocks and includes a plurality of driving units cascaded in series. Each driving unit is for driving a load and includes an input terminal, an output terminal, a first switch and a second switch. The first switch has a first terminal coupled to the input terminal, a second terminal coupled to a first node, and a control terminal receiving a first clock, and the first switch is turned on when the first clock is at high level. The second switch has a first terminal receiving a second clock, a second terminal coupled to the output terminal, and a control terminal coupled to the first node, wherein the second clock charges and discharges the load through the second switch when the first node is at high level; wherein the output terminal of each driving unit is coupled to the input terminal of the immediately succeeding driving unit.

Abstract: An image reading apparatus includes a sheet conveyance path on which a sheet of a document from which an image is to be read is conveyable; a light source that emits light to be irradiated on the sheet; a conductive unit through which heat generated at the light source is transferable; and a heat radiating unit that forms a part of the sheet conveyance path, through which the heat transferred from the light source to the conductive unit is propagable, and that radiates the heat propagated from the conductive unit to air flowing in the sheet conveyance path when the sheet is being conveyed.

Abstract: An absorbent article comprising nonwoven fabric having convex and concave surfaces, and that allows liquid such as excreta and the like to permeate quickly. A sanitary napkin has a plurality of raised ridge portions and groove portions in a top sheet member. The fiber density of the side edge portions of each of the plurality of raised ridge portions in the thickness direction of the nonwoven fabric is substantially uniform, and is higher than the average fiber density in the raised ridge portions. The fiber density of the central portion between both the side edge portions of each of the plurality of raised ridge portions is substantially uniform in the thickness direction of the nonwoven fabric, and is lower than the average fiber density in the raised ridge portions.

Abstract: The present invention relates to power supplies, and more particularly, to a power supply having a maximum power point tracking function that can reduce manufacturing costs and circuit size by using a maximum power point tracking section with a simplified circuit in a solar photovoltaic power generator supplying power using sunlight instead of using a micro controller, the maximum power point tracking section that controls power switching according to a result of integration of a value obtained by dividing a power variation by a voltage variation to track a maximum power value.

Abstract: A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer.

Abstract: An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the memory array. A second power line is coupled with the second switch. The second power line is operable to supply a second power voltage for retaining the data during a retention mode. A third power line is coupled with the memory array. The third power line is capable of providing a third power voltage.

Abstract: The invention relates to synchronization applied to a data stream structured as super-frames. Each block in a super-frame comprises a slow synchronization part and at least one traffic frame. The slow synchronization parts in the super-frame result at least from a decomposition of a synchronization management word. Additional synchronization parts similar to the slow synchronization parts and distributed in place of traffic frame bits in the super-frame are inserted in the super-frame. The invention provides for fast synchronization coexisting with a pre-existing slow synchronization without increasing the bandwidth. The invention is particularly applicable to cryptographic synchronization between fixed and/or mobile terminal equipments operating in interconnected dissimilar networks whose synchronization time constants differ.

Abstract: A method for dummy metal and dummy via insertion is provided. In one embodiment, dummy metals are inserted using a place and route tool, where the place and route tool has timing-awareness. Then, dummy vias arrays are inserted inside an overlap area of dummy metals using a design-rule-checking utility. Fine-grained dummy vias arrays are inserted in available space far away from main patterns. The dummy-patterns resulting from the inserted dummy vias are compressed using the design-rule-checking utility to reduce the size of a graphic data system file generated from the integrated circuit design. The dummy vias can be inserted with relaxed via spacing rules. The dummy metals are inserted with a constant line-end spacing between them for better process control and the maximum length of the dummy metal can be limited for smaller coupling effects. The dummy vias can have various sizes and a square or rectangular shape.

Abstract: A superconducting cable terminal connection device connecting a terminal of a superconducting cable for power transmission to an external power system, includes: an electric field relaxation shield disposed inside an insulation housing; a horizontal conductor fixed to an end portion of a core of the superconducting cable drawn into the electric field relaxation shield; an insulator which coats an outer periphery of the horizontal conductor; a vertical conductor which is drawn into the electric field relaxation shield and has a through-hole through which the horizontal conductor and the insulator pass so as to be slidable in a lengthwise direction; and a flexible electrical conduction member which electrically connects an end portion of the horizontal conductor to the vertical conductor.

Abstract: The present invention relates to a signal sequence peptide for the improvement of extracellular secretion efficiency of a heterologous protein in E. coli. More particularly, the present invention relates to a gene construct for the improvement of extracellular secretion efficiency of the said heterologous protein in E. coli, which comprises a polynucleotide encoding a recombinant protein composed of the heterologous protein linked to C-terminal of the signal sequence peptide represented by SEQ. ID. NO. 3. The present invention contributes to the improvement of extracellular secretion efficiency of a recombinant protein, so that it can be effectively applied to the production of a recombinant protein.

Abstract: In a GaN-based semiconductor device, an active layer of a GaN-based semiconductor is formed on a silicon substrate. A trench is formed in the active layer and extends from a top surface of the active layer to a depth reaching the silicon substrate. A first electrode is formed on an internal wall surface of the trench and extends from the top surface of the active layer to the silicon substrate. A second electrode is formed on the active layer to define a current path between the first electrode and the second electrode via the active layer in an on-state of the device. A bottom electrode is formed on a bottom surface of the silicon substrate and defines a bonding pad for the first electrode. The first electrode is formed of metal in direct ohmic contact with both the silicon substrate and the active layer.

Abstract: A memory circuit includes a plurality of bit lines. A first memory cell and a second memory cell are coupled in series. Each of the first memory cell and the second memory cell is capable of storing a first type datum. The first memory cell and the second memory cell share a first common source/drain (S/D) region. The first common S/D region is electrically isolated from all of the bit lines.

Abstract: A joint on an aircraft, the joint comprising: a first component; a second component joined to the first component; and a bonding lead which forms an electrical connection between the components with a resistance between 100 k? and 10 M?. Surprisingly, it has been found that a bonding lead with a relatively high resistance can be used without seriously compromising the static discharge performance of the bonding lead, and that the resulting comparatively low flow of current reduces the risk of sparking in the event of an lightning strike. Bonding leads may be provided as a kit of parts in which at least two of the bonding leads have different lengths and the longer lead is formed from a material having a higher bulk conductivity than the shorter lead. Thus the bonding leads can be made with approximately similar resistances regardless of their lengths.

Abstract: Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height.

Abstract: A method for high-resolution timing measurement includes a first oscillator generating a first clock with a first frequency. A second oscillator generates a second clock with a second frequency. A delay pulse generator generates a delayed pulse from the second clock. An oscillator tuner controls the second frequency to be as close as possible to the first frequency without being the same as the first frequency. A sampling module samples the delayed pulse at the first frequency. A counter generates a digital counter value by counting a number of samples made by the sampling module.

Abstract: A surface emitting laser apparatus includes an arithmetic processing unit including an I/O unit for externally inputting an instruction and a core unit that performs an operation based on the instruction and outputs a differential voltage signal modulated with a predetermined amplitude according to a result of the operation, capacitors respectively arranged on output paths of the differential voltage signal, and a surface emitting laser device that is directly connected to the arithmetic processing unit via the capacitors. An I/O voltage and a core voltage are externally supplied to the I/O unit and the core unit, respectively. The arithmetic processing unit generates a driving voltage signal by superimposing the differential voltage signal with the core voltage commonly supplied as a bias voltage without stepping up or down the core voltage and without amplifying the differential voltage signal and supplies the driving voltage signal to the surface emitting laser device.

Abstract: A process for differentiating conductive and/or ferromagnetic objects (O) in a material stream (2) comprises generating an electromagnetic alternating field by exciting a coil (S) with a sinusoidal voltage (ue(t)) of a constant frequency (fM), detecting an impedance change in the coil, which has been caused by an object (O), by determining at least one pair of values from a peak value (ÎM) and a phase shift (?m) of the coil current (iM(t)) toward the excitation potential (ue(t)) of the coil, and determining the material by comparing the peak values (ÎM) and phase shifts (?m) with reference values, wherein the peak values (ÎM) of the coil current (iM(t)) are calculated at at least one measuring phase angle (?m) with the aid of a window comparator having a constant window width (?i), wherein the time (?tM) between the window inlet point (p4) and the window outlet point (p6) of the coil current (iM(t)) is measured and the gradient of the current profile (iM(t)) is calculated from the window width (?i) and the me