Abstract: In an MOS integrated circuit device, a multilayer polysilicon/metallic-silicide gate-level metallization structure is patterned to form gates and associated interconnects. Some of the interconnects are designed to make contact with ohmic regions in the single-crystalline body of the device. In accordance with a simplified fabrication procedure, a single implantation step is utilized to dope the metallic silicide while doping selected portions of the body. During a subsequent heating step, source, drain and ohmic contact regions are formed in the body. During the same step, the dopant in the metallic silicide diffuses into underlying layers of polysilicon and into body portions directly underlying polysilicon in amounts sufficient to render the polysilicon conductive and to form additional ohmic contact regions in the body.

Abstract: In a conventional CMOS integrated circuit such as a switched capacitor filter, power supply noise signals are coupled from the substrate to high impedance nodes via various parasitic capacitances. To minimize these noise signals and thereby improve the power supply rejection ratio of the circuit, only N-channel transistors are coupled to the nodes. Additionally, the P-tubs of these transistors are connected to an on-chip regulated power supply. Moreover, for certain metallic runners and capacitors of the circuit that are connected to the specified nodes and parasitically coupled to the substrate, grounded P-tubs are formed directly under the runners and capacitors.

Abstract: In a plasma-assisted etching apparatus and method designed to pattern silicon dioxide in a plasma derived from a mixture of trifluoromethane and ammonia, surfaces in the reaction chamber are coated with a layer of silicon. Contamination of wafers during the etching process is thereby substantially reduced. In practice, this leads to a significant increase in the yield of acceptable chips per wafer.

Abstract: The manufacture of VLSI devices is facilitated by a method for chlorine reactive sputter etching of silicon materials in a plasma reactor that has been passivated by a previous etching operation involving a fluorine-containing gas. The passivated reactor is reactivated for chlorine reactive sputter etching by the generation of a boron trichloride plasma in the reactor. In the preferred embodiment, a mixture of boron trichloride and chlorine is used to initiate the etching of the silicon material before pure chlorine is used to complete the etch. The invention permits silicon materials to be etched in a reactor in which chlorine and fluorine-containing gases are used sequentially.

Abstract: In a plasma-assisted etching apparatus and method designed to pattern aluminum or polysilicon, surfaces in the reaction chamber are coated with a layer of aluminum oxide. Contamination of wafers during the etching process is thereby substantially reduced. In practice, this leads to a significant increase in the yield of acceptable chips per wafer.

Abstract: In a fabrication sequence for VLSI MOS devices, an advantageous alignment mark for a wafer to be directly processed by electron beam lithography is made of tantalum disilicide protected by a silicon nitride layer.

Abstract: In a plasma-assisted dry etching process designed to pattern VLSI devices, a relatively high and uniform etch rate exhibiting low contamination is achieved over the entire surface extent of each wafer to be etched. This is accomplished by mounting the wafers in a unique fashion on one of two spaced-apart electrodes in the reaction chamber of a dry etching system. In particular, the front surface of each wafer is maintained in substantially the same plane as that of surrounding dielectric material. Additionally, the thickness of the surrounding dielectric material is designed to be considerably greater than the thickness of any dielectric material in contact with the back surface of each wafer. In that way, the entire front surface extent of each wafer is influenced by a relatively uniform electric field. Moreover, the available field in the chamber is in effect focussed onto the wafer surfaces, thereby achieving a relatively high etch rate characterized by low contamination.

Abstract: The present invention is a method and apparatus for aligning a semiconductor wafer to be patterned by a step-and-repeat photolithographic system. The inventive alignment technique, which is able to compensate for local wafer tilt and/or nonuniform photoresist thickness, is applicable to semiconductor wafers which have, on a surface portion, one or more Fresnel zone plate alignment marks.

Abstract: In a plasma-assisted etching apparatus and method, surfaces in the reaction chamber are covered with a layer of a polyarylate polymer. Contamination of wafers during the etching process is thereby substantially reduced. In practice, this leads to a significant increase in the yield of acceptable chips per wafer.

Abstract: For a given resolution or address dimension, the pattern-writing speed of an electron beam exposure system is increased by utilizing a new mode of raster scanning. In the new mode, the writing spot dimensions of the electron beam are varied rapidly during the scan. In an electron column designed for variable-spot raster scanning, an illuminated aperture is demagnified to form the writing spot. By imaging a first aperture upon a second aperture and rapidly deflecting the image of the first aperture, the portion of the second aperture that is illuminated by the electron beam is altered. In that way, the spot size is selectively varied in a high-speed way during the raster scanning process.

Abstract: At least one chip on a multiple-chip integrated circuit wafer is dedicated for use as a test device for checking mask level-to-level misalignment. The test device is made during the same fabrication sequence in which the circuit-containing chips are made. No additional processing steps are required for the test device. By forming unique S-shaped members in each test device and establishing electrical contact therewith, a sensitive electrical tester is provided for indicating level-to-level registration in the circuit-containing chips.

Abstract: In a chlorine plasma, reactive sputter etching of monocrystalline silicon, undoped polycrystalline silicon or doped polycrystalline silicon is achieved. The etching processes are substantially free of any loading effects and are characterized by high resolution, excellent uniformity and high selectivity with respect to, for example, silicon dioxide. For silicon and undoped polysilicon, the edge profile of the etched material is anisotropic. For doped polysilicon, the edge profile can be controlled to occur anywhere in the range from completely isotropic to completely anisotropic.

Abstract: It is known to deposit a refractory metal silicide on a polysilicon gate layer to form a low-resistivity composite structure. For VLSI MOS devices, very-high-resolution patterning of the composite structure is required. In accordance with this invention, a silicide pattern is formed on polysilicon by a lift-off technique. In turn, the patterned silicide is utilized as a mask for anisotropic etching of the underlying polysilicon. High-conductivity composite silicide-on-polysilicon gate structures for VLSI MOS devices are thereby achieved.

Abstract: Light-activated power FETs (18, 20, 80, 82) are utilized as switching elements in DC-to-DC converters. The FETs are characterized by high speed and low losses. As a result, the converters are capable of providing very low DC voltages in an efficient low-cost way.

Abstract: In an integrated circuit fabrication sequence, a hardened mask pattern adhered to an underlying substrate is removed from the substrate by a solvent that comprises anhydrous hydrazine and dimethyl sulfoxide. The solvent rapidly penetrates the interface between the pattern and the underlying substrate and quickly breaks the adhesive bonds therebetween. Other materials (e.g., Al, Si, SiO.sub.2) in the structure being fabricated are not deleteriously affected by the solvent.

Abstract: In a VLSI device fabrication process, erosion of a patterned resist layer (16, 18) during dry etching of an underlying layer (14) can significantly limit the high-resolution patterning capabilities of the process. As described herein, a protective polymer layer (60, 62) is formed and maintained only on the resist material (16, 18) while the underlying layer (14) is being etched. High etch selectivities are thereby achieved. As a consequence, very thin resist layers can be utilized in the fabrication process and very-high-resolution patterning for VLSI devices is thereby made feasible.

Abstract: The problem of reliably adhering resists to underlying surfaces made of, for example, phosphorus-doped silicon dioxide or silicon nitride is a particularly difficult one. In practice, the use of standard adhesion promoters such as HMDS provides only marginal relief. By baking a relatively thin layer of resist on the underlying layer, a tenacious bond between the thin layer and the underlying surface is achieved. Subsequently, a relatively thick layer of resist is applied and patterned in a standard way. An excellent bond between the thick and thin resist layers results. Subsequent processing of the patterned thick layer leaves the two noted bonded interfaces virtually intact.

Abstract: Zone plate patterns (12,20,61,62) formed on spaced-apart mask and wafer members (10,60) are utilized for alignment purposes in the fabrication of integrated circuits. By providing off-axis illumination of the patterns, a significant mask-to-wafer alignment capability is provided in an X-ray lithographic system. This capability includes being able to correct for so-called magnification errors that arise from physical distortions in the mask and/or wafer or in other components of the system. These errors are compensated for by utilizing the zone plate patterns to form alignment marks that serve as a basis for adjusting the mask-to-wafer separation.

Abstract: A high-throughput apparatus is utilized in a process for sputter etching or reactive sputter etching of wafers. The apparatus comprises a large-area electrode centrally disposed within a relatively small-area cylindrical electrode. Wafers to be etched are mounted on the inside surface of the cylindrical electrode. A source of a-c power is capacitively coupled to the cylindrical electrode and the center electrode is grounded. By establishing a suitable plasma within the apparatus, simultaneous anisotropic etching of multiple wafers can be achieved.

Abstract: An apparatus and method for holding a thin workpiece such as a semiconductor wafer for operations which require the workpiece to have a high degree of planarity such as photolithographic printing includes positioning the workpiece onto a planar holding face comprising the points of a multiplicity of regularly spaced-apart substantially parallel pins with a thin rim encompassing all pins to contain a vacuum in the region adjacent to the workpiece. The small abutting area of each pinpoint abutment reduces the probability of dirt particles collecting on the holding face and provides a high thrust pressure to dislodge dirt particles interposed between the abutment and the workpiece. A small amount of lateral motion is imparted to the workpiece when it first contacts the holding face to brush off any dirt particles on the abutments.