Patents Represented by Attorney, Agent or Law Firm Majestic, Parsons, Siebert & Hsue
  • Patent number: 6310436
    Abstract: A light transmitting container is used to house a cold cathode fluorescent lamp (CCFL) to reduce heat loss and to increase the luminous efficiency of the lamp. An electrical connector configuration is connected to an electrode of the lamp and adapted to be electrically and mechanically connected to a conventional electrical socket. A driver circuit in the container converts 50 or 60 Hz power to the high frequency power suitable for operating the CCFL. At least one of the electrodes of the CCFL is outside of the container to facilitate heat dissipation. A two-dimensional array of CCFLs may be held by a module housing to form a display for displaying still or moving images and characters. The above-described CCFL configurations may also be used for displaying traffic information.
    Type: Grant
    Filed: May 6, 1998
    Date of Patent: October 30, 2001
    Assignee: GL Displays, Inc.
    Inventors: Xiaoqin Ge, Shichao Ge, Victor Lam, Yiping Ge
  • Patent number: 6211612
    Abstract: A monochromic, multi-color and full-color cold cathode fluorescent display (CFD), comprises of some shaped white or multi-color or red, green blue color cold cathode fluorescent lamps (CCFL), reflector, base plate, temperature control means, luminance and contrast enhancement face plate, shades and its driving electronics. CFD is a large screen display device which has high luminance, high efficiency, long lifetime, high contrast and excellent color. CFD can be used for both outdoor and indoor applications even at direct sunlight, to display a character, or graphic and video image.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: April 3, 2001
    Assignee: GL Displays, Inc.
    Inventor: Xiaoqin Ge
  • Patent number: 6184772
    Abstract: A chip thermistor has a pair of outer electrodes opposite each other with a specified distance in between on one of the surfaces of a thermistor element and an inner electrode extending inside the thermistor element so as to overlap these outer electrodes in the direction perpendicular to the surface on which the outer electrodes are formed. An electrically insulating layer is preferably formed on the same surface as and between the pair of outer electrodes. Each of the outer electrodes may be formed with two or more layers, the outermost of the layers being of gold.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: February 6, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masahiko Kawase, Norimitsu Kitoh
  • Patent number: 6184984
    Abstract: A polarized sample beam of broadband radiation is focused onto the surface of a sample and the radiation modified by the sample is collected by means of a mirror system in different planes of incidence. The sample beam focused to the sample has a multitude of polarization states. The modified radiation is analyzed with respect to a polarization plane to provide a polarimetric spectrum. Thickness and refractive information may then be derived from the spectrum. Preferably the polarization of the sample beam is altered only by the focusing and the sample, and the analyzing is done with respect to a fixed polarization plane. In the preferred embodiment, the focusing of the sample beam and the collection of the modified radiation are repeated employing two different apertures to detect the presence or absence of a birefringence axis in the sample. In another preferred embodiment, the above-described technique may be combined with ellipsometry for determining the thicknesses and refractive indices of thin films.
    Type: Grant
    Filed: February 9, 1999
    Date of Patent: February 6, 2001
    Assignee: Kla-Tencor Corporation
    Inventors: Shing Lee, Haiming Wang, Adam Norton, Mehrdad Nikoonahad
  • Patent number: 6185119
    Abstract: An integrated circuit memory is capable of storing analog information without the need for A/D conversion. Samples of a analog signal input are stored in nonvolatile memory cells. The integrated circuit is also capable of storing digital information in digital form. The sampling rate at which the analog signal input is sampled is user selectable. An internal signal path of the integrated circuit memory is differential, which enhances the precision with which the analog signal is stored in the memory cells.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: February 6, 2001
    Assignee: SanDisk Corporation
    Inventors: Andreas M. Haeberli, Carl W. Werner, Hock C. So, Sau C. Wong, Cheng-Yuan Michael Wang, Leon Sea Jiunn Wong
  • Patent number: 6184726
    Abstract: Level shifter circuits are used to configure analog or multilevel memory cells. A level shifter circuit generates an output voltage that is above the input voltage by an offset voltage value. The magnitude of this offset voltage or the relationship between the input and output voltages of the level shifter is adjustable or programmably selectable. Adjustments can be made after the integrated circuits is fabricated and packaged. Adjustments are made by configuring bits of data in the integrated circuit to indicate the offset voltage or other parameters. These configuration bits are implemented using latches, flip-flops, registers, memory cells, or other storage circuits.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: February 6, 2001
    Assignee: SanDisk Corporation
    Inventors: Andreas M. Haeberli, Carl W. Werner, Cheng-Yuan Michael Wang, Hock C. So, Leon Sea Jiunn Wong, Sau C. Wong
  • Patent number: 6184095
    Abstract: A method is provided to fabricate a mask ROM device via a medium current implanter. For fabricating the mask ROM device, first, formation of an array of MOS transistors on a semiconductor substrate is achieved. Each of the MOS transistors includes a gate oxide film, a gate electrode, a source region and a drain region. After the formation of the array of transistors, a USG layer, a BPSG layer, metal electrodes and a passivation layer are sequentially formed. After an order from client, an etching back process is performed to remove selected portions of the passivation layer to form openings in accordance with a ROM code. The selected portions are located over the selected gate electrodes respectively. The portions of the BPSG layer within the openings are successively etched until the remained BPSG layer is in a predetermined thickness. Finally, ROM code ions are implanted into the substrate via a medium current implanter through the openings.
    Type: Grant
    Filed: February 9, 1999
    Date of Patent: February 6, 2001
    Assignee: Windbond Electronics Corp.
    Inventors: Chen-Jui Lee, Min-Hsiu Chen
  • Patent number: 6181599
    Abstract: Program disturb in a Flash storage array is reduced by applying a voltage level that depends on the threshold level of a previously programmed cell to the word-line of that cell during programming of subsequent cells on the same bit-line. By applying higher voltages to word-lines containing unselected programmed memory cells with higher threshold voltages, program disturb due to these higher threshold cells is reduced.
    Type: Grant
    Filed: April 13, 1999
    Date of Patent: January 30, 2001
    Assignee: SanDisk Corporation
    Inventor: Geoff Gongwer
  • Patent number: 6177991
    Abstract: A measuring device such as a spectrometer uses an automatic sample changer for carrying a plurality of samples. The automatic sample changer may include a rotary circular disk rotatable around its central shaft by a stepping motor for changing positions of the samples which are positioned in a circle around the central shaft of the disk. A memory device preliminarily storing control data for each of different kinds of automatic sample changers is provided. The automatic sample changer, when connected to a control unit in the main body, serves to receive control signals for controlling motions of the motor and to transmit data stored in the memory device through a connector. The main body of the measuring device contains a control unit which serves to read out the control data from the memory device, to use the received control data to generate the control signal and to transmit the generated control signal to the automatic sample changer.
    Type: Grant
    Filed: November 9, 1998
    Date of Patent: January 23, 2001
    Assignee: Shimadzu Corporation
    Inventor: Tetsuo Okuda
  • Patent number: 6176921
    Abstract: A cement dispersant composed of water-soluble vinyl copolymers which include specified kinds of constituent units at specified ratios and of which the weight average molecular weight pullulan converted by GPC method is 15000-150000 and the ratio of weight average molecular weight to number average molecular weight is 2-7 is used together with cement, aggregates and water to produce concrete with the water-to-cement ratio of 20-45%.
    Type: Grant
    Filed: February 17, 1999
    Date of Patent: January 23, 2001
    Assignee: Takemoto Yushi Kabushiki Kaisha
    Inventors: Mitsuo Kinoshita, Kazuhisa Okada, Masahiro Iida
  • Patent number: 6174695
    Abstract: The present invention provides methods of treating inflammatory diseases mediated by poly-unsaturated lipid metabolites by inhibiting epoxide hydrolase, methods for assaying or screening the epoxide hydrolase inhibitors for inhibitory specificity and for toxicity, and novel biologically active tetrahydrofuran diols of arachidonic acid, including antibodies thereto.
    Type: Grant
    Filed: May 14, 1999
    Date of Patent: January 16, 2001
    Assignee: The Regents of the University of California
    Inventors: Bruce D. Hammock, Mehran F. Moghaddam, Jeffrey M. Cheek, Babak Borhan, James Fergusson, David F. Grant, Jessica F. Greene, Kazuhiko Matoba, Jiang Zheng, Marlene F. Sisemore
  • Patent number: 6172817
    Abstract: A non-phase separable glass material for fabricating a GRIN lens comprises 5-20 mole % boron oxide and ratio R of network modifiers in mole % to the network former boron oxide in mole % is in the range of about 1-1.5. The melted preform of such glass material is extruded through an opening to form a glass rod where the extrusion process eliminates bubbles that may be present in the preform. Neodymium oxide may be added in the frit material for forming the preform to reduce friction forces in the extrusion process and reduces the stress in the glass rod. Centerless grinding may be performed to control the diameter and roughness of the surface of the rod to control the diffusion parameters during the subsequent ion-exchange.
    Type: Grant
    Filed: April 13, 2000
    Date of Patent: January 9, 2001
    Assignee: Dicon Fiberoptics, Inc.
    Inventors: Udayan Senapati, Ho-Shang Lee
  • Patent number: 6172592
    Abstract: A chip-type thermistor has a pair of electrically conductive planar comb-shaped surface electrodes facing each other on one of principal surfaces of a thermistor block, and an insulating layer covers these surface electrodes. A pair of outer electrodes are formed on end surfaces of the thermistor block, each electrically connected to an associated one of the surface electrodes.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: January 9, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hidehiro Inoue, Mitsuaki Fujimoto, Yuichi Takaoka
  • Patent number: 6170267
    Abstract: A sample cooler has a thermostatic chamber containing a heat-conducting block on which vessels containing liquid samples are set. A control unit activates a cooling mechanism of the air cooling type to cool the air inside the thermostatic chamber. Thereafter, when the temperature or humidity inside the thermostatic chamber is detected to have reached a specified level, when condensation of dew is detected inside the thermostatic chamber, or when a predetermined time has elapsed, the control unit starts to operate another cooling mechanism of the direct cooling type to cool the heat-conducting block, such that the samples can be cooled directly and quickly under a dehumidified condition without causing dew condensation.
    Type: Grant
    Filed: July 15, 1999
    Date of Patent: January 9, 2001
    Assignee: Shimadzu Corporation
    Inventor: Mitsuo Kitaoka
  • Patent number: 6169503
    Abstract: Converters such as digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) use conversion arrays containing non-volatile memory cells to provide references that depend on the threshold voltages of the memory cells. The array contains sets (for example, rows) of the memory cells where each memory cell in a set corresponds to a digital value and has a threshold voltage that is equal to the analog voltage mapped to the digital value. An ADC applies an analog input signal to the gates of reference cells in a set and generates a digital signal according to which of the memory cells conduct. The ADC does not require comparators and has a low circuit area, low power consumption, and high speed. A DAC selects a memory cell corresponding to a digital input value and reads the memory cell to generate an analog output signal equal to the threshold voltage of the memory cell. An ADC and a DAC can use the same conversion array to ensure that the ADC inverts the conversion that the DAC performs.
    Type: Grant
    Filed: September 23, 1998
    Date of Patent: January 2, 2001
    Assignee: SanDisk Corporation
    Inventor: Sau C. Wong
  • Patent number: 6169820
    Abstract: The present invention relates to processes for compressing data and to corresponding systems. The data to be compressed may here be analog or digital speech and image data, or may be any data provided by computers.
    Type: Grant
    Filed: August 5, 1996
    Date of Patent: January 2, 2001
    Assignee: TECOMAC AG
    Inventors: Michael R. Wade, Arthur G. Sutsch
  • Patent number: 6165846
    Abstract: The improvement of thin tunnel oxides used in EEPROM and FLASH tecnologies using post-oxidation annealing in nitrogen causes defects in subsequent oxide films. These are manifested by oxide thinning at the bird's beak and result in high gate leakage. As the time and temperature to the post-oxidation annealing are increased for improved tunnel oxide performance, the number of defects increases rapidly. A method of realizing the improved tunnel oxide Q.sub.BD using higher post-oxidation time and temperature annealing while at the same time not degrading the quality of subsequent gate oxides is shown. The use of sacrificial oxidation and strip just prior to the transistor gate oxidation is described. This process removes the additional nitride which exists at the field edges, leading to the oxide thinning. As a result, improved tunnel oxide integrity can be achieved without degradation of high and low voltage transistors.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: December 26, 2000
    Assignee: Zilog, Inc.
    Inventors: Timothy K. Carns, John A. Smythe, III, John A. Ransom, Bernice L. Kickel, John E. Berg
  • Patent number: 6166938
    Abstract: Input partitioning logic is coupled to bit-lines of a content addressable memory (CAM) array having four-transistor (4-T) non-volatile Flash CAM cells. Prior to a program or search operation on the 4-T Flash CAM cells, two input data bits and their complements are applied to the input partitioning logic, which can be two-input NAND, NOR, AND, or OR gates. By selecting the appropriate values for the input bits, individual ones of the memory cells in the 4-T CAM cell can be programmed, or a desired two-bit pattern can be searched. The use of input partitioning logic prior to applying the search and program voltages to the bit-lines of the CAM cell results in substantially less voltage transitions during searches and less required programming current because fewer Flash memory cells are required to be programmed. Consequently, power consumption while operating the CAM array is substantially reduced, and the Flash memory cell endurance is effectively increased.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: December 26, 2000
    Assignee: SanDisk Corporation
    Inventor: Sau-Ching Wong
  • Patent number: 6166606
    Abstract: A phase locked loop is described for generating an output clock signal that is both synchronizing with a synchronizing signal and oscillating at substantially the same frequency as required by the system. The phase locked loop as disclosed compares the time durations of the output clock of a voltage-controlled oscillator with the system clock for N cycles. A correction signal is then generated by comparing these two time durations, and the correction signal is fed back to the voltage-controlled oscillator to eliminate the difference in the time durations. In addition, the voltage-controlled oscillator is also synchronized with the synchronizing signal by using the synchronizing signal as a reset.
    Type: Grant
    Filed: February 10, 1999
    Date of Patent: December 26, 2000
    Assignee: Zilog, Inc.
    Inventor: Anatoliy V. Tsyrganovich
  • Patent number: 6163246
    Abstract: A chip-type electronic device has a sintered ceramic body formed by integrally sintering a plurality of ceramic layers, inner electrodes including first electrodes, second electrodes and a third electrode formed inside this sintered ceramic body and outer electrodes formed on both end surfaces of this sintered ceramic body. One end of each of the first electrodes is electrically connected to one of the outer electrodes. Each of the second electrodes is electrically connected to a corresponding one of the first electrodes through an associated one of throughholes through one of the ceramic sheets. The third electrode is electrically connected to the other of the outer electrodes and overlaps with the second electrodes as seen perpendicularly to the planar inner electrodes.
    Type: Grant
    Filed: May 31, 2000
    Date of Patent: December 19, 2000
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yukiko Ueda, Masahiko Kawase