Abstract: A method 100, an apparatus, and a computer program product for constructing a runtime symbol table SymTbl[ ] for a computer program are disclosed. In the method, a symbol table SymTbl[ ] for storing one or more entities Ei is initialized 110. One or more tickets Ti are then added 120 into the symbol table SymTbl[ ] for each entity Ei that does not already exist in the symbol table SymTbl[ ]. An offset address is then inserted 130 after a predefined token “>” for each ticket Vi in a predefined set V of tickets in the symbol table SymTbl[ ] characterized as a sequence of the tickets Vi. One or more preassigned addresses are also inserted 140 in the symbol table SymTbl[ ] for each ticket Vi in the set V of tickets that has preassigned addresses.

Abstract: A method, an apparatus, and a computer program product are disclosed for detecting memory-related errors in a computer program during compiling of the computer program. In the method, static analysis is performed upon a computer program. One or more conditions in the computer program are computed based on the static analysis. Each condition is a test for checking a memory access in the computer program and can be either a pre- or post-condition. The validity of each condition in the computer program is then evaluated. If the evaluation is determinate during compiling, the presence or absence of memory-related errors in the computer program is reported. A condition is determinate if the condition is valid or invalid during compiling. Otherwise, computer code based on the condition is generated for incorporation in the computer program for run-time detection of memory-related errors.

Abstract: A data network may comprise routers for transmitting data between locations in the network via alternative routes. A network gateway or server may normally send data packets to a particular default router but, for network communication recovery, the gateway needs to select a new default route if the first goes down. The recovery method of this invention comprises storing information indicative of respective ones of a plurality of said alternative routes; accessing the stored information to identify a first of said routes; directing data to the router means for the data to be transmitted to the said another location via the first route; sensing failure of said transmission and, in the event of such failure, accessing said stored information to identify a second of said alternative routes; and directing data to the router means for the data to be transmitted to the said another location via the second route.

Abstract: A method and computer program product for executing procedure calls, such as procedure calls in the C programing language. For a procedure call, reference parameters are identified, and replaced by respective scalar variables. The scalar values are propagated to a call site and directly accessible by the calling procedure body. As such, the scalar variables are global in scope.

Abstract: This invention relates to a method, apparatus and program product for transmitting email to selected recipients defined by one or more aliases in identified lists of recipients, by providing transmission control directives given by the user, parsing the said directives, expanding aliases wherever necessary and applying each directive to the identified lists of recipients.

Abstract: A method, an apparatus, and a computer program product for optimising a bus in a Processor Local Bus (PLB) system are disclosed. A master engine performs a transfer transaction of N bytes of data on the bus of the PLB system. A type of read or write data transfer to be performed by the master engine is determined to optimize operation of the bus in response to a transfer request received asynchronously from a device coupled to the bus. This involves a request type determination function. Data is asynchronously transferred using a FIFO between the device and the bus dependent upon the determined type of transfer.

Abstract: A method and system for analysing software to estimate the cost of production, development and maintenance of computer applications. Unlike previous proposals for such analysis, where the primary measured parameters are the numbers of lines of code and function points, the inventive method identifies high complexity software segments arising from specific discontinuities in execution of the program, ie points at which the program has to, in effect, make decisions. These items are assigned complexity indices which may be summed to give an overall complexity value for the program or the indices may be displayed as a histogram showing the complexity distribution of the program.

Abstract: A dual master apparatus for mastering a Processor Local Bus (PLB), which is a high-performance, on-chip bus used in many System on Chip (SOC) applications, supporting up to 16 masters. The apparatus includes a first circuit for generating an address phase for read data coupled to the PLB, and a second circuit for generating an address phase for write data coupled to the PLB. The second address phase generating circuit is adapted to carry out a write operation when the write data bus is idle and the read data bus is busy, and vice versa. The first and second address phase generating circuits can simultaneously process read and write requests. The apparatus also may include circuits for handling read and write data coupled to the first and second address generating circuits, respectively. Further, the apparatus may include circuits for requesting read and write data coupled to the read- and write-data handling circuits, respectively.

Abstract: The interface method invocation mechanism of the present invention includes an interface method table (IMT) for a given class of objects. The IMT comprises a table of entries each corresponding to a set S of interface methods that are implemented by objects of the given class. The entries of the IMT are used to support invocation of interface methods. More specifically, processing of a method invocation statement involves either I) loading the pointer to the implementation of the interface method from an entry of the IMT and passing control to this implementation; or II) loading the pointer to a conflict resolution routine pointed by an IMT entry and passing control to this conflict resolution routine.

Abstract: The present invention enables re-ordering of instructions to be executed while assuring a precise exception. In Java language, an optimization process of re-ordering instructions to be executed is performed by Just-In-Time compiler. For instance, the instructions lining in order from instruction E1 which was moved forward to instruction S2which had been located before E1 is registered as interrupt inhibited section R1, and from instruction S4 which was moved forward to instruction S3 which had been located before S4 is registered as interrupt inhibited section R2 (S is an instruction which has an affect observable from the outside at the execution, and E is an instruction which may cause an exception). Also, in FIG. 7, S4 which was an instruction behind E1 in the original order is registered as R1's instruction invalid at an exception. If E1 causes an exception, an interrupt handler is activated and the instructions of interrupt inhibited section R1 are copied to another area.

Abstract: A method for performing remote calls between source and target computing machines includes running a program thread on the source machine which invokes a remote call to the target machine. The remote call is transmitted to the target machine, the call including an identifier associated with the program thread. A response to the remote call is received from the target machine, the response including the identifier, whereby the response is returned to the program thread on the source machine using the identifier.

Abstract: An optical device with a defined total device stress (&sgr;10) and a therefrom resulting defined birefringence in order to obtain a well defined optical polarization dependence is proposed. It comprises a lower cladding layer (3) with a first refractive index (n3), thereon an upper cladding layer (5) with a second refractive index (n5) and between an optical waveguide core (4) with a third refractive index (n4) which is bigger than the first refractive index (n3) and the second refractive index (n5). The optical waveguide core (4) has a waveguide core stress (&sgr;4) resulting from the manufacturing process and the upper cladding layer (5) is manufactured to have an inherent cladding layer stress (&sgr;5) which together with the waveguide core stress (&sgr;4) results in the total device stress (&sgr;10).

Abstract: A method of controlling packet traffic in an IP network of originating, receiving and intermediate nodes to meet performance objectives established by service level agreements. Traffic statistics and performance data such as delay and loss rates relating to traffic flows are collected at intermediate nodes. A control server processes the collected data to determines data flow rates for different priorities of traffic. A static directory node is used to look up inter-node connections and determine initial traffic classes corresponding to those connections. The rates are combined with the initial traffic classes to define codes for encoding the headers of packets to determine their network priority.

Abstract: A sub-0.1 &mgr;m MOSFET device having minimum poly depletion, salicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene-gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.

Abstract: A high-aspect ratio resist profile is obtained using a development process wherein a mixture of an alcohol and water is used as the developer. The alcohol/water mixture is non-toxic, and does not cause excess swelling and cracking of the resist during the development process.

Abstract: A strained Si CMOS structure is formed by steps which include forming a relaxed SiGe layer on a surface of a substrate; forming isolation regions and well implant regions in said relaxed SiGe layer; and forming a strained Si layer on said relaxed SiGe layer. These processing steps may be used in conjunction with conventional gate processing steps in forming a strained MOSFET structure.

Abstract: The geometric processing of an ordered sequence of graphics commands is distributed over a set of processors by the following steps. The sequence of graphics commands is partitioned into an ordered set of N subsequences S0 . . . SN−1, and an ordered set of N state vectors V0 . . . VN−1 is associated with said ordered set of subsequences S0 . . . SN−1. A first phase of processing is performed on the set of processors whereby, for each given subsequence Sj in the set of subsequences S0 . . . SN−2, state vector Vj+1 is updated to represent state as if the graphics commands in subsequence Sj had been executed in sequential order. A second phase of the processing is performed whereby the components of each given state vector Vk in the set of state vectors V1 . . . VN−1 generated in the first phase is merged with corresponding components in the preceding state vectors V0 . . .

Abstract: A terminology extraction system which allows for automatic creation of bilingual terminology has a source text which comprises at least one sequence of source terms, aligned with a target text which also comprises at least one sequence of target terms. A term extractor builds a network from each source and target sequence wherein each node of the network comprises at least one term and such that each combination of source terms is included within one source node and each combination of target terms is included within one target node. The term extractor links each source node with each target node, and through a flow optimization method selects relevant links in the resulting network. Once the term extractor has been run on the entire set of aligned sequences, a term statistics circuit computes an association score for each pair of linked source/target terms, and finally the scored pairs of linked source/target term that are considered relevant bilingual terms are stored in a bilingual terminology database.

Abstract: A semiconductor device such as a P-N or P-I-N junction diode, includes a first semiconductor layer having a first conductivity-type and being mounted over a metal address line, and a second semiconductor layer having a second conductivity-type and being mounted over the first semiconductor material. The diode preferably has a thickness of substantially no more than about 1 micron, and the diode includes a P-N junction confined to a thickness of less than about 0.1 micron. In the preferred embodiment the method comprises depositing a first semiconductor layer having a first conductivity type, depositing a second intrinsic layer, annealing to convert both layers to a polycrystalline layer, implanting ions of a second conductivity type into the second layer, and annealing to convert the second layer to a polycrystalline. The result is a diode having an ultra-sharp p-n junction.

Abstract: Backup copying of designated datasets representing a first selected point in time consistency may be performed in a data processing system on an attached storage subsystem concurrent with data processing system application execution by first suspending application execution only long enough to form a logical-to-physical address concordance, and thereafter physically backing up the datasets on the storage subsystem on a scheduled or opportunistic basis. An indication of each update to a selected portion of the designated datasets which occurs after the first selected point in time is stored and application initiated updates to uncopied designated datasets are first buffered. Thereafter, sidefiles are made of the affected datasets, or portions thereof, the updates are then written through to the storage subsystem, and the sidefiles written to an alternate storage location in backup copy order, as controlled by the address concordance.