Patents Represented by Attorney, Agent or Law Firm Manny W. Schecter
  • Patent number: 6515957
    Abstract: Ferroelectric thin films can hold non-volatile memories with bit sizes down to 30 nm at room temperature. This invention provides a data storage system that preferably comprises an electrically conducting rotatable hard disk substrate having a ferroelectric storage layer that comprises storage cells which can be written and read along concentric recording tracks, a pivoted servo arm with a free end for movement across the recording tracks. The free end of the servo arm includes both a write head, consisting of an electrically conducting tip, and a read head, consisting of a field effect transistor (FET), held close to the disk surface. The FET has a gate electrode and is positioned on the servo arm with the gate electrode held close to the ferroelectric surface of the disk during read operations of the data storage system. Read and write operations can be performed with standard semiconductor technologies in combination with existing magnetic hard-disk servo-control architecture.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: February 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: Dennis M. Newns, Jonathan Z. Sun
  • Patent number: 6504173
    Abstract: The present invention is directed to a method of fabricating a dual gate structure for use in FET devices wherein the dual gate structure comprises a bottom gate that is substantially a mirror image of the top gate. The method utilizes a shallow trench isolation process for the purpose of planarization and gate alignment. Also disclosed is a dual gate structure which is fabricated utilizing the method of the present invention.
    Type: Grant
    Filed: January 9, 2001
    Date of Patent: January 7, 2003
    Assignee: International Business Machines Corporation
    Inventors: Louis Lu-Chen Hsu, Li-Kong Wang
  • Patent number: 6501895
    Abstract: An optical device with a defined total device stress (&sgr;10) and a therefrom resulting defined birefringence in order to obtain a well defined optical polarization dependence is proposed. It comprises a lower cladding layer (3) with a first refractive index (n3), thereon an upper cladding layer (5) with a second refractive index (n5) and between an optical waveguide core (4) with a third refractive index (n4) which is bigger than the first refractive index (n3) and the second refractive index (n5). The optical waveguide core (4) has a waveguide core stress (&sgr;4) resulting from the manufacturing process and the upper cladding layer (5) is manufactured to have an inherent cladding layer stress (&sgr;5) which together with the waveguide core stress (&sgr;4) results in the total device stress (&sgr;10).
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: December 31, 2002
    Assignee: International Business Machines Corporation
    Inventors: Peter Bloechl, Gian-Luca Bona, Roland W. Germann, Horst Folkert, Illana Massarek, Bert Jan Offrein, Huub L. Salemink, Dorothea W. Wiesmann
  • Patent number: 6470494
    Abstract: This invention relates to the loading of classes in programming environments, and in particular, Java programming environments. This invention discloses a system and method that permits dynamic loading of classes during the execution of Java programs. This invention allows for classes to be loaded despite the fact that such classes may not reside in the current path or working directory within a Java programming environment. This invention also discloses a system and method for archiving files in an archive file that provides customized entry names for the archived files.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: October 22, 2002
    Assignee: International Business Machines Corporation
    Inventors: Victor S. Chan, Shirley S. Chiang, David K. Stokes, Leonard W. Theivendra
  • Patent number: 6459682
    Abstract: A method of controlling packet traffic in an IP network of originating, receiving and intermediate nodes to meet performance objectives established by service level agreements. Traffic statistics and performance data such as delay and loss rates relating to traffic flows are collected at intermediate nodes. A control server processes the collected data to determines data flow rates for different priorities of traffic. A static directory node is used to look up inter-node connections and determine initial traffic classes corresponding to those connections. The rates are combined with the initial traffic classes to define codes for encoding the headers of packets to determine their network priority.
    Type: Grant
    Filed: April 7, 1998
    Date of Patent: October 1, 2002
    Assignee: International Business Machines Corporation
    Inventors: Edward James Ellesson, Roch Andre Guerin, Sanjay Damodar Kamat, Arvind Krishna, Rajendran Rajan, Dinesh Chandra Verma
  • Patent number: 6453380
    Abstract: In a system in which data are stored in an interleaved fashion in a memory consisting of a plurality of memory banks, a method and means are provided for mapping a given address into a memory bank and an internal memory bank address. Lookup table means (LUT1; LUT2) are provided for furnishing not only a bank number but also a part (MSP) of the internal bank address, in response to selected portions (X, Y) from the given address, while the remainder (LSP) of the internal bank address is directly taken from the given address. Two implementations are disclosed in which either two lookup tales are provided, or two sections in a single lookup table, for separately generating the bank number and a part of the internal bank address. Another implementation provides two lookup tables which are accessed sequentially and which provide different intermediate outputs (m, n, p, q, r) which are selectively combined (B, C) to obtain bank number as well as part of the internal bank address.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: September 17, 2002
    Assignee: International Business Machines Corporation
    Inventor: Jan Van Lunteren
  • Patent number: 6440808
    Abstract: A sub-0.1 &mgr;m MOSFET device having minimum poly depletion, salicided source and drain junctions and very low sheet resistance poly-gates is provided utilizing a damascene-gate process wherein the source and drain implantation activation annealing and silicidation occurs in the presence of a dummy gate region which is thereafter removed and replaced with a polysilicon gate region.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: August 27, 2002
    Assignee: International Business Machines Corporation
    Inventors: Diane Catherine Boyd, Stephen Bruce Brodsky, Hussein Ibrahim Hanafi, Ronnen Andrew Roy
  • Patent number: 6440639
    Abstract: A high-aspect ratio resist profile is obtained using a development process wherein a mixture of an alcohol and water is used as the developer. The alcohol/water mixture is non-toxic, and does not cause excess swelling and cracking of the resist during the development process.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: August 27, 2002
    Assignee: International Business Machines Corporation
    Inventors: Robert E. Fontana, Jr., Jordan A. Katine, Ernst Kratschmer, Michael J. Rooks, Ching H. Tsang, Raman Gobichettipalayam Viswanathan
  • Patent number: 6429061
    Abstract: A strained Si CMOS structure is formed by steps which include forming a relaxed SiGe layer on a surface of a substrate; forming isolation regions and well implant regions in said relaxed SiGe layer; and forming a strained Si layer on said relaxed SiGe layer. These processing steps may be used in conjunction with conventional gate processing steps in forming a strained MOSFET structure.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: August 6, 2002
    Assignee: International Business Machines Corporation
    Inventor: Kern Rim
  • Patent number: 6426012
    Abstract: A three-part etching process is employed to selectively pattern exposed magnetic film layers of a magnetic thin film structure. The magnetic structure to be etched includes at least one bottom magnetic film layer and at least one top film layer which are separated by a tunnel barrier layer. The three-part etching process employs various etching steps that selective removing various layers of the magnetic thin film structure stopping on the tunnel barrier layer. The first etching step selective removes any surface oxide that may be present in the passivating layer that is formed on the top magnetic thin film layer, the second etching step selectively removes portions of the passivating layer and the third etching step selectively removes a portion of the exposed magnetic film layer of the structure stopping on the tunnel barrier layer.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: July 30, 2002
    Assignee: International Business Machines Corporation
    Inventors: Eugene John O'Sullivan, Alejandro Gabriel Schrott
  • Patent number: 6427154
    Abstract: The present invention relates to a method of delaying space allocation for parallel copying garbage collection in a data processing system comprising a memory divided in a current area (from-space) used by at least a program thread during current program execution and reserve area (to-space), and wherein a copying garbage collection is run in parallel by several collector threads, the garbage collection consisting in stopping the program threads and flipping the roles of the current area and reserved area before copying into the reserved area the live objects stored in the current area.
    Type: Grant
    Filed: August 2, 2000
    Date of Patent: July 30, 2002
    Assignee: International Business Machines Corporation
    Inventors: Elliot K. Kolodner, Erez Petrank
  • Patent number: 6384833
    Abstract: The geometric processing of an ordered sequence of graphics commands is distributed over a set of processors by the following steps. The sequence of graphics commands is partitioned into an ordered set of N subsequences S0 . . . SN−1, and an ordered set of N state vectors V0 . . . VN−1 is associated with said ordered set of subsequences S0 . . . SN−1. A first phase of processing is performed on the set of processors whereby, for each given subsequence Sj in the set of subsequences S0 . . . SN−2, state vector Vj+1 is updated to represent state as if the graphics commands in subsequence Sj had been executed in sequential order. A second phase of the processing is performed whereby the components of each given state vector Vk in the set of state vectors V1 . . . VN−1 generated in the first phase is merged with corresponding components in the preceding state vectors V0 . . .
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: May 7, 2002
    Assignee: International Business Machines Corporation
    Inventors: Monty Montague Denneau, Peter Heiner Hochschild, Henry Stanley Warren, Jr.
  • Patent number: 6236958
    Abstract: A terminology extraction system which allows for automatic creation of bilingual terminology has a source text which comprises at least one sequence of source terms, aligned with a target text which also comprises at least one sequence of target terms. A term extractor builds a network from each source and target sequence wherein each node of the network comprises at least one term and such that each combination of source terms is included within one source node and each combination of target terms is included within one target node. The term extractor links each source node with each target node, and through a flow optimization method selects relevant links in the resulting network. Once the term extractor has been run on the entire set of aligned sequences, a term statistics circuit computes an association score for each pair of linked source/target terms, and finally the scored pairs of linked source/target term that are considered relevant bilingual terms are stored in a bilingual terminology database.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: May 22, 2001
    Assignee: International Business Machines Corporation
    Inventors: Jean-Marc Lange, Eric Gaussier
  • Patent number: 6180444
    Abstract: A semiconductor device such as a P-N or P-I-N junction diode, includes a first semiconductor layer having a first conductivity-type and being mounted over a metal address line, and a second semiconductor layer having a second conductivity-type and being mounted over the first semiconductor material. The diode preferably has a thickness of substantially no more than about 1 micron, and the diode includes a P-N junction confined to a thickness of less than about 0.1 micron. In the preferred embodiment the method comprises depositing a first semiconductor layer having a first conductivity type, depositing a second intrinsic layer, annealing to convert both layers to a polycrystalline layer, implanting ions of a second conductivity type into the second layer, and annealing to convert the second layer to a polycrystalline. The result is a diode having an ultra-sharp p-n junction.
    Type: Grant
    Filed: February 18, 1998
    Date of Patent: January 30, 2001
    Assignee: International Business Machines Corporation
    Inventors: Stephen McConnell Gates, Roy Edwin Scheuerlein
  • Patent number: 5539914
    Abstract: A method and system are disclosed for efficiently reading and processing multiple data blocks stored in a removable data storage medium within a data storage system, wherein each data block includes a header portion containing selected parameters necessary to identify and process an associated data block, and a data portion. Each data block is accessed within the removable data storage medium utilizing track logic circuitry and then coupled to a data block buffer for temporary storage. A header processing logic circuit is interposed between the track logic circuitry and the data block buffer and is utilized to initiate processing of only the header portion of each data block prior to storage of the data block within the data block buffer. After completion of processing of the header portion of a data block and completion of storage of that data block within the data block buffer, the data block is efficiently processed utilizing selected parameters contained within the header portion.
    Type: Grant
    Filed: June 14, 1993
    Date of Patent: July 23, 1996
    Assignee: International Business Machines Corporation
    Inventors: Scott M. Fry, Habib M. Torab
  • Patent number: 5530601
    Abstract: A method and apparatus for detecting peaks in a signal which comprises an alternating polarity waveform including a plurality of points. A selected point in the signal is designated. Thereafter, a threshold value for the selected point is established utilizing a prior threshold value associated set off with spaces with a point prior to the selected point as follows:(m(n)=t0*ax(n)+t1*m(n-1)wherein n is the point identifier, m(n) is the threshold value, t0 is a fixed positive constant less than one, t1 is a fixed positive constant less than one, ax(n) is the absolute value of the input signal, and m(n-1) is the prior threshold value for the prior point. In this manner the threshold value may be adjusted for fluctuations in amplitude of the signal. Next, the selected point is compared with the threshold value to determine whether or not the selected point is within a predetermined distance of the threshold.
    Type: Grant
    Filed: September 30, 1993
    Date of Patent: June 25, 1996
    Assignee: International Business Machines Corporation
    Inventors: Robert A. Hutchins, Ara S. Patapoutian
  • Patent number: 5508855
    Abstract: A method and apparatus for detecting peaks in a signal which comprises an alternating polarity waveform including a plurality of points. A selected point in the signal is designated. Thereafter, a threshold value for the selected point is established utilizing a prior threshold value associated set off with spaces with a point prior to the selected point as follows:(m(n)=t0*ax(n)+t1*m(n-1))wherein n is the point identifier, m(n) is the threshold value, t0 is a fixed positive constant less than one, t1 is a fixed positive constant less than one, ax(n) is the absolute value of the input signal, and m(n-1) is the prior threshold value for the prior point. In this manner the threshold value may be adjusted for fluctuations in amplitude of the signal. Next, the selected point is compared with the threshold value to determine whether or not the selected point is within a predetermined distance of the threshold.
    Type: Grant
    Filed: April 7, 1995
    Date of Patent: April 16, 1996
    Assignee: International Business Machines Corporation
    Inventors: Robert A. Hutchins, Ara S. Patapoutian
  • Patent number: RE37038
    Abstract: A method in a data processing system for automatically terminating or resuming backup copy sessions after an abnormal interrupt or reset notification occurrence during a backup copy process. A status indication is entered into activity tables associated with a plurality of storage subsystems and devices within a data processing system in response to initiation of a backup copy session. Status indications are then entered upon successful completion of a backup copy session within the data processing system. The indications within the activity tables are reviewed to determine the status of a backup copy session upon restarting a resource manager, abnormal termination of a backup copy program, or an operating system initial program load. If a backup copy session has been initiated but not completed, the backup copy session is then terminated. The indications within the activity tables are also reviewed to determine the status of a backup copy session if a reset notification is raised by a storage subsystem.
    Type: Grant
    Filed: August 31, 1995
    Date of Patent: January 30, 2001
    Assignee: International Business Machines Corporation
    Inventors: Lawrence E. Eastridge, Robert Frederic Kern, William Frank Micka, Claus William Mikkelsen, James Mitchell Ratliff
  • Patent number: RE37601
    Abstract: Backup copying of designated datasets representing a first selected point in time consistency may be performed in a data processing system on an attached storage subsystem concurrent with data processing system application execution by first suspending application execution only long enough to form a logical-to-physical address concordance, and thereafter physically backing up the datasets on the storage subsystem on a scheduled or opportunistic basis. An indication of each update to a selected portion of the designated datasets which occurs after the first selected point in time is stored and application initiated updates to uncopied designated datasets are first buffered. Thereafter, sidefiles are made of the affected datasets, or portions thereof, the updates are then written through to the storage subsystem, and the sidefiles written to an alternate storage location in backup copy order, as controlled by the address concordance.
    Type: Grant
    Filed: November 15, 1995
    Date of Patent: March 19, 2002
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Elwood Eastridge, Robert Frederic Kern, James Mitchell Ratliff
  • Patent number: RE36864
    Abstract: The invention is a positive peak level comparator for generating a positive peak pulse when a TES (Tracking Error Signal) is higher than a predetermined positive level, a negative peak level comparator for generating a negative peak pulse when the TES is lower than a predetermined negative level, and a logic circuit for generating an output pulse when said positive peak pulse and said negative peak pulse have been alternately input thereto. The arrangement prevents the TES from being miscounted even if the TES is distrubed due to the occurrence of, for example, a noise at a level close to either said predetermined positive level or said predetermined negative level and either said peak pulse or said negative pulse is successively generated.
    Type: Grant
    Filed: April 28, 1995
    Date of Patent: September 12, 2000
    Assignee: International Business Machines Corporation
    Inventors: Naoyuki Kagami, Hiroaki Kubo, Keiichi Okada