Patents Represented by Attorney, Agent or Law Firm Marc A. Ehrlich
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Patent number: 6029261Abstract: The invention relates to a test circuit and a test system which provides interconnect test capability for modules and boards. The test circuit comprises a plurality of scan chains, including a plurality of registers. The registers in each module or board are logically sorted such that identical registers are arranged successively.Type: GrantFiled: November 24, 1997Date of Patent: February 22, 2000Assignee: International Business Machines CorporationInventor: Wilfred Hartmann
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Patent number: 6023702Abstract: The inventive concept comprises a system platform for a synergistic, role modular work process environment. A work process object (WPO) (1001) is created, residing in a data base, and stored in a memory of the process and project management computer system (1030). All data concerning the process and project management are reported to said work process object (WPO) (1001) and said work process object (WPO) (1001) is used as a common data base. According to the inventive concept, each view must be supported by a specific workplace, represented by digital data and enforcing the rules for the specific role. A work process information model supports the dynamic definition and use of a data base object representing a work process, boch in its process and project planning modes and its execution. According to the inventive concept, one object supports simultaneously all modes delimited by dynamically moving boundaries. Workplace implementation enforces over-all rules for each role in the inventive system.Type: GrantFiled: December 10, 1998Date of Patent: February 8, 2000Assignee: International Business Machines CorporationInventors: Udo Leisten, Ekkehard Voesch, Geoff Parncutt, Kurt Bandat
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Patent number: 6021442Abstract: A method, associated apparatus and program product for partitioning a plurality of interconnection elements among disjoint partitions of processors in a computer system so as to interconnect the processors within each of the disjoint partitions, and to isolate the processors in each interconnected partition from processors in the other partitions. The interconnection elements may be arranged into groups including node coupling elements and link coupling elements and in larger systems may include intermediate groups having intermediate coupling elements.Type: GrantFiled: July 17, 1997Date of Patent: February 1, 2000Assignee: International Business Machines CorporationInventors: Aruna V. Ramanan, Mark Gurevich, Leroy R. Lundin, David G. Folsom, Kevin J. Reilly, Mark G. Atkins, Robert F. Bartfai
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Patent number: 6018817Abstract: A method and apparatus are described for providing error correcting code (ECC) which may be incorporated into a computer system which includes one of a plurality of memory configurations and which may include a pre-existing error control feature. A data store operation causes the receipt of a word including data bits and check bits generated by a pre-existing error control feature. The data and check bits of the received word are used to generate additional check bits based upon the configuration of the computer system memory. The additionally generated check bits are stored in the memory along with the received word. Upon a subsequent data fetch operation which retrieves the word and check bits the check bits are decoded thereby providing error detection and correction in the retrieved word for single and multiple bit errors including the failure of an entire memory chip.Type: GrantFiled: December 3, 1997Date of Patent: January 25, 2000Assignee: International Business Machines CorporationInventors: Chin-Long Chen, Timothy Jay Dell, Wayne C. Kwan
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Patent number: 6014756Abstract: A high availability shared cache memory in a tightly coupled multiprocessor system provides an error self-recovery mechanism for errors in the associated cache directory or the shared cache itself. After an error in a congruence class of the cache is indicated by an error status register, self-recovery is accomplished by invalidating all the entries in the shared cache directory means of the accessed congruence class by resetting Valid bits to "0" and by setting the Parity bit to a correct value, wherein the request for data to the main memory is not cancelled.Multiple bit failures in the cached data are recovered by setting the Valid bit in the matching column to "0". The processor reissues the request for data, which is loaded into the processor's private cache and the shared cache as well. Further requests to this data by other processors are served by the shared cache.Type: GrantFiled: December 16, 1996Date of Patent: January 11, 2000Assignee: International Business Machines CorporationInventors: Gerhard Dottling, Klaus-Jorg Getzlaff, Bernd Leppla, Wille Udo
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Patent number: 6009548Abstract: A method and apparatus are described for providing error correcting code (ECC) which may be incorporated into a computer system which includes one of a plurality of memory configurations and which may include a pre-existing error control feature. A data store operation causes the receipt of a word including data bits and check bits generated by a pre-existing error control feature. The data and check bits of the received word are used to generate additional check bits based upon the configuration of the computer system memory. The additionally generated check bits are stored in the memory along with the received word. Upon a subsequent data fetch operation which retrieves the word and check bits the check bits are decoded thereby providing error detection and correction in the retrieved word for single and multiple bit errors including the failure of an entire memory chip.Type: GrantFiled: June 18, 1998Date of Patent: December 28, 1999Assignee: International Business Machines CorporationInventors: Chin-Long Chen, Timothy Jay Dell, Wayne C. Kwan
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Patent number: 6009261Abstract: Provides a program translation and execution method which stores target routines (for execution by a target processor) corresponding to incompatible instructions, interruptions and authorizations of an incompatible program written for execution on another computer system built to a computer architecture incompatible with the architecture of the target processor's computer system. The disclosed process allows the target processor to emulate incompatible acts expected in the operation of an incompatible program when the target processor itself is incapable of performing the emulated acts. Each of the instructions, interruptions and authorizations found in the incompatible programs has one or more corresponding target routines, any of which may need to be preprocessed before it can precisely emulate the execution results required by the incompatible architecture.Type: GrantFiled: December 16, 1997Date of Patent: December 28, 1999Assignee: International Business Machines CorporationInventors: Casper Anthony Scalzi, Eric Mark Schwarz, William John Starke, James Robert Urquhart, Douglas Wayne Westcott
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Patent number: 5999960Abstract: Described is a floating point processor comprising a multiply section and an add section, for performing a multiplication-add operation comprised of a multiplication operation prior to an addition operation which is using the result of the multiplication operation. The floating point processor comprises a multiply add controller (MAC1) which receives signals representing the exponents of the operands for the multiplication-add operation and signals representing the leading zero digits of an un-normalized result of the multiplication operation. The floating point processor further comprises a pair of shift units, (AL1, BN1), one receiving the un-normalized result of the multiplication operation and the other the operand to be added thereto. The multiply add controller (MAC1) determines shift values (Block.sub.-- Norm.sub.-- Value, AL1.sub.-- Align.sub.Type: GrantFiled: December 16, 1996Date of Patent: December 7, 1999Assignee: International Business Machines CorporationInventors: Gunter Gerwig, Michael Kroner
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Patent number: 5996063Abstract: The invention relates to the area of register renaming and allocation in superscalar computer systems. When a multitude of instructions in the instruction stream reads from or writes to a certain logical register, said logical register will have to be represented by a multitude of physical registers.Therefore, there have to exist several physical rename registers per logical register. The oldest one of said rename registers defines the architected state of the computer system, the in-order state.The invention provides a method for administration of the various register instances. Both the registers representing the in-order state and the various rename instances are kept in one common circular buffer. There exist two pointers per logical register: The first one, the in-order pointer, points to the register that represents the in-order state, the second one, the rename pointer, points to the most recent rename instance.Type: GrantFiled: March 11, 1997Date of Patent: November 30, 1999Assignee: International Business Machines CorporationInventors: Ute Gaertner, Klaus Jorg Getzlaff, Thomas Koehler, Erwin Pfeffer
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Patent number: 5982899Abstract: A method for verification of configuration data which is expressive of the configuration of a computer system. A computer system having configuration data stored therein, further includes an identifier for uniquely identifying the computer system. A copy of the stored configuration data is encoded via an encoding method which uses the identifier, and the encoded configuration data is encrypted via an encryption method which uses a private key. Subsequently, the encrypted configuration data is decrypted via a decryption method using a public key producing a decrypted result. The decrypted result may either be decoded using the identifier and compared to the stored configuration data or alternatively the stored configuration data may be encoded using the identifier and compared to the decrypted result.Type: GrantFiled: December 16, 1996Date of Patent: November 9, 1999Assignee: International Business Machines CorporationInventor: Jurgen Probst
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Patent number: 5978957Abstract: A shifting structure and method which separates a shifting operation into partial shifts which may be executed in different pipeline staged is described herein. In a first pipe stage, an operand is read out and at least one partial shift is accomplished by placing the operand or parts thereof into registers coupled to a shift unit. The shift unit, in a second pipe stage, finalizes the shifting operation executing the remaining partial shifts, thereby reducing the time required for the total shifting operation. A control string is derived in the shift unit based on the shift amount to correct the output of the shifted result as well as providing for parity prediction therefor.Type: GrantFiled: July 14, 1997Date of Patent: November 2, 1999Assignee: International Business Machines CorporationInventors: Wilhelm Haller, Klaus Getzlaff, Erwin Pfeffer, Ute Gaertner, Gunter Gerwig
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Patent number: 5974543Abstract: An apparatus and a method for performing subroutine call and return operations in a computer having a processor with an instruction prefetch mechanism which includes a branch history table for storing target addresses of a plurality of branch instructions found in an instruction stream. The branch history table 22 contains a potential call instruction tag 37 and a return instruction tag 39. For each potential subroutine call instruction found in a prefetch instruction stream an address pair containing the call target address and the next sequential instruction address of the instruction is stored in a return identification stack 24. Subsequently detected branch instructions initiate an associative search on the next sequential instruction part in the return identification stack where a matching entry identifies the branch instruction as a return instruction. The address pair contained in the matching entry is then transferred to a return cache 30 which is arranged in parallel to the branch history table.Type: GrantFiled: February 17, 1998Date of Patent: October 26, 1999Assignee: International Business Machines CorporationInventors: Rolf Hilgendorf, Oliver Laub, Hans-Werner Tast
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Patent number: 5968137Abstract: A method for testing protocol converters is presented, which permits the achievement of a test of all commands, independently of a corresponding test system. A modified protocol converter itself is used for the test. With the help of this method, a test for conversion of data structures can be carried out, of a slow protocol into the corresponding data structures of a fast protocol in the original speed.Type: GrantFiled: August 4, 1997Date of Patent: October 19, 1999Assignee: International Business Machines CorporationInventors: Frank D. Ferraiolo, Don T. Gottstine, Jurgen Hass, Joseph B. Hanley, Thomas H. Hillock, Donald Jung
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Patent number: 5956563Abstract: The invention relates to a method for reducing a transient thermal mismatch between a first component and a second component which are in mechanical contact with one another. The temperature of the first component is controlled by the amount of energy dissipated thereby. The amount of energy dissipated is controlled as a function of a data pattern input into the first component which causes a certain number of gates within the component to switch per clock cycle. By determining the desired energy dissipation in terms of the number of gates which are to be switched and arranging the input data pattern accordingly, the thermal mismatch between the components may be reduced.Type: GrantFiled: January 9, 1997Date of Patent: September 21, 1999Assignee: International Business Machines CorporationInventors: Erich Klink, Dietmar Schmunkamp, Helmut Weber, Roland Frech, Bernd Garben, Hubert Harrer
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Patent number: 5948060Abstract: Speeds up a commanded system to read or write data for a large number of data frames transmitted on a link by executing a TRANSFER STRUCTURE instruction that automatically controls the reading or writing of a large number of scattered storage blocks in the storage of the commanded system containing, or to contain, the data transmitted on the link.Type: GrantFiled: January 24, 1997Date of Patent: September 7, 1999Assignee: International Business Machines CorporationInventors: Thomas Anthony Gregg, Kulwant Mundra Pandey
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Patent number: 5944797Abstract: The present invention significantly reduces or eliminates the involvment of central processors in the message block handling of received communication-link responses within a Central Processing Complex (CPC). When a commanding system sends a command, it must receive a response frame from the commanded system indicating if the command was correctly received or not. A significant amount of time is required for the commanding system processor to move the received response frame from a receiving link buffer to an area in the CPC memory. The preferred embodiment avoids the need for having a commanding system processor either wait for or be interrupted to handle the response frame. The preferred embodiment provides advanced preparation of a data mover in a manner to enable the data mover in the computer system to handle the reception of each response frame without involving the commanding system processor.Type: GrantFiled: May 28, 1997Date of Patent: August 31, 1999Assignee: International Business Machines CorporationInventors: Thomas Anthony Gregg, Kulwant Mundra Pandey
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Patent number: 5944772Abstract: A combined adder and logic unit having a reduced operation delay of arithmetic and logic operations, and providing an improved fan in and reduced wiring delays and capacity if implemented in the arithmetic and logic section of a microprocessor chip. The unit comprises a carry network (30) connected to operand inputs for generating carry-out signals of the byte positions (By0-By7) and further comprises a pre-sum logic (32) having a bit function generator (42) and a sum generator (45, 46, 48). Said bit function generator derives from the operands Ai and Bi bit functions Gi, Pi which are provided as logic function output and as input to said sum generator for producing preliminary arithmetic functions (SUM0, SUM1) to anticipate carry-in signals of one or zero.Type: GrantFiled: November 13, 1997Date of Patent: August 31, 1999Assignee: International Business Machines CorporationInventors: Juergen Haas, Wilhelm Haller, Ulrich Krauch, Thomas Ludwig, Holger Wetter
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Patent number: 5938786Abstract: An apparatus and method is provided for asynchronously transmitting data across fiber optical cables in a serial manner. Frames are provided as a mechanism to transmit associated data over a serial link and to tie the data being transmitted to a particular buffer set. Each outstanding request for each buffer set is individually timed to detect lost frames, and each buffer set maintains a state that keeps track of the progress and sequence of received frames. When transmission errors occur in the frames, the errors may affect only the information field in which case there is enough information in the header to identify the frame. If a frame is damaged, any outstanding operations for the affected buffer set are cleared, and any commands are brought to a logical ending point. The computer system which originates the frames is then notified of the specific nature of the error, and which information is supplied to help the originating computer system efficiently conclude the recovery procedure.Type: GrantFiled: November 30, 1995Date of Patent: August 17, 1999Assignee: International Business Machines CorporationInventor: Thomas Anthony Gregg
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Patent number: 5937199Abstract: A method and apparatus for implementing a user programmable interrupt mask and timeout count. A master mask latch receives non-privileged instructions which alternatively cause the latch to disable and enable interrupt requests for the processor. The non-privileged disable interrupts instruction additionally causes the initiation of a timeout counter for defining the duration of an interval for which interrupt requests may be disabled. The non-privileged enable interrupts instruction additionally terminates the count of the timeout counter. If the timeout counter is not halted within the defined interval, a system error interrupt is generated, interrupts are re-enabled and the counter is halted. In a further embodiment, the disable interrupts instruction may be incorporated into a fetch and hold instruction and the enable interrupts instruction may be incorporated into a store and release instruction to facilitate atomic read, modify, write operations.Type: GrantFiled: June 3, 1997Date of Patent: August 10, 1999Assignee: International Business Machines CorporationInventor: Joseph L. Temple
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Patent number: 5930491Abstract: A method for addressing internal instructions in an out-of-order processor is proposed, which allows for an efficient register renaming even in case internal instructions are issued to a multitude of window buffers. In this case, it is not clear how internal instructions that stem from one external instruction can be indicated as being "related". In the method proposed, a common instruction identifier is assigned to each of the internal instructions of a group of internal instructions representing an external instruction. Furtheron, an offset identifier is assigned to each of said internal instructions in order to be able to unambiguously identify each of said internal instructions. These two identifiers are used as a tag, in order to be able to resolve data dependencies. By use of the invention, exception handling, recovery of mispredicted branches, and committing related instructions corresponding to one external instruction is simplified.Type: GrantFiled: June 20, 1997Date of Patent: July 27, 1999Assignee: International Business Machines CorporationInventors: Rolf Hilgendorf, Wolfram Sauer, Hartmut Schwermer