Abstract: A method and apparatus for emulating a high storage capacity DRAM component. The emulation involves the use of a component containing multiple DRAMs, each having a lower storage capacity than that of the emulated DRAM, but having a cumulative storage capacity greater than or equal to that of the DRAM being emulated. Emulation entails the decoding of extra bits in an address signal from a controller for the high capacity DRAM to direct the output of DRAM control signals from a decoder to the multiple DRAM component so as to activate only one of the plurality of lower density DRAMs therein. Advantageously, the invention may be implemented so as to permit migration to a next generation DRAM device without altering wiring on the printed circuit board or changing the memory controller used to access the DRAM component.

Abstract: A computer system employs a repeater unit which repowers a serial channel link. The repeater unit also monitors and records non-idle usage and errors for both directions of the repeated serial link. Non-idle usage of the serial link is recorded as a number of seconds that non-idle traffic flowed in the link over a given period of time. Link serial code violations and loss-of-light transitions are also counted. Link code violations are counted with an accuracy that permits targeted serial link bit-error rates, of no more than one bit error in approximately two months, to be accurately verified for the first time in a normal customer environment. The repeater unit permits an attached monitoring computer to read and reset all its usage and error counters as often as required by the customer, and without losing any counts of any counted event.

Abstract: A method and system for the design verification of logic units capable of providing verification of a logic unit design prior to chip production. At least one test unit is coupled to a logic unit via an interface. The test unit includes a set of operations which are applied to the logic unit. The selection of test operations to be applied to the logic unit and the determination of the start times thereof are executed randomly and independently of each other. Thus, with the present method and system two parameters of the test operation generating event: the sequence of the test operations, and the temporal relationship between the test operations, are independently and randomly modified.

Abstract: A method for operating an apparatus including a DRAM with a computer system having a PCMCIA interface. The method includes the steps of converting the PCMCIA SRAM control signals sent by the computer system across the PCMCIA interface into DRAM control signals, so as to permit the communication of data and control signals between the computer system and the DRAM device. The method further includes refreshing the DRAM device and arbitrating between the refreshing of the DRAM and providing for communication between the DRAM and the computer system. The method further teaches providing power management functions required for operating a DRAM device in a PCMCIA environment.

Abstract: The screen display scale is changed in an easy and intuitive manner, without intermediate steps or operations, and without taking up additional screen display area. At least one so-called scroll bar must be displayed on the screen and be functional at any time that the scale could be changed by the user. Additional function is loaded onto screen scroll bars to support the change of scale function as well as the scrolling function. The scroll bar is composed of a bar and a slider, and the slider position and size respectively indicate the location of working area relative to the virtual screen and the relative size of the working area as a function of the total size of the virtual screen area. Scrolling, or panning, is accomplished by moving the slider within the bar. In addition, the size of the slider can be changed in order to effect a change in the scale of the working area, thereby providing a zoom function for the scroll bar.

Abstract: A system for the transmission of information between elements of a data processing complex and a method for establishing such a system. Two elements of a data processing system are connected by a physical link comprising multiple conductors attached to transceivers at channels in each data processing element. Once the transceivers have been synchronized, commands and responses are exchanged which ensure that all of the transceivers in a channel are connected to the same channel on the other end of the conductor. If the transceivers are considered configured an entry is made in a Configured-Transceiver table. A search is made of an Allowed-Operational-Link table which contains sets of transceivers which are allowed to become operational links. The set of transceivers thus found, is compared against the Configured-Transceiver-Table to verify that all of the members of the set have been configured. If a match is found, this set of transceivers becomes an Intended-Operational-Link.

Abstract: A computer system employs a repeater unit which repowers a serial channel link. The repeater unit also monitors and records non-idle usage and errors for both directions of the repeated serial link. Non-idle usage of the serial link is recorded as a number of seconds that non-idle traffic flowed in the link over a given period of time. Link serial code violations and loss-of-light transitions are also counted. Link code violations are counted with an accuracy that permits targeted serial link bit-error rates, of no more than one bit error in approximately two months, to be accurately verified for the first time in a normal customer environment. The repeater unit permits an attached monitoring computer to read and reset all its usage and error counters as often as required by the customer, and without losing any counts of any counted event.