Abstract: An ultrasound diagnosing apparatus comprises an ultrasound transducer for emitting ultrasound beams and receiving reflected beams to form a scanning plane, and for displacing the scanning plane three-dimensionally for N steps; image data processor for obtaining predetermined brightness value data of respective echoes of the received ultrasound beams which define the respective scanning plane and for outputting the brightness value data of the ultrasound beams of the respective scanning plane as one pixel line data; a memory for storing ultrasound image data of M number of ultrasound images into M number of frames, the ultrasound image data of each of the M number of ultrasound images being comprised of N number of the pixel line data produced by the image data processor; writing control circuit for sequentially storing M number of the pixel line data each having a different time phase to the corresponding positions of the respective frames of the memory, the M number of the pixel line data being obtained by c

Abstract: The system for creating a custom golf scorecard comprises a computer interface for receiving a user selection of one of a predetermined plurality of scorecard designs and user input textual data. The design selection, the textual data and a file name to identify the user together form a preliminary digital scorecard specification. The system includes a memory or storage device having a set of image placeholders and associated representative images which can be assigned to certain panels of the user's custom designed golf scorecard. Exemplary representative images include a digital image of a selected portion of a generic golf course, a generic graphical logo, a generic photograph, or a generic computer generated map of a golf course. A complete digital scorecard specification is generated via a computer which integrates together image placeholders and associated representative images selected from the storage device, the design selected by the user, and the textual data input by the user.

Abstract: A power factor correction circuit for a boost-type voltage converter determines the input voltage by sensing the rate at which the current through an inductor changes when a switching transistor is turned on. The circuit includes a current sense circuit which generates a control signal in response to the current flowing in the inductor. The control signal is compared with a sawtooth signal to control the input current waveform. An output detecting circuit generates a comparison reference signal for regulating the output voltage of the converter. The comparison reference signal is summed with the control signal to provide a comparison signal. A comparison circuit compares the comparison signal with the sawtooth signal and generates a pulse width modulated signal for controlling the switch. A compensation signal generator generates a compensated comparison signal in response to a ripple component in the output signal of the converter.

Abstract: A method is provided for forming planar, self-aligned spaced-apart wells without a high temperature oxidation step to form an ion barrier. The method comprises preparing a substrate with a silicon dioxide-polysilicon-silicon dioxide barrier layer that can be etched to expose different sublayers of the barrier at selected junctures in the production process. A single masking step defines the location of a first set of wells on the prepared substrate. The outer silicon dioxide layer is etched to expose the polysilicon layer at the selected locations, and the substrate is implanted to form the first set of wells. Following ion implantation, the substrate photo-resist is removed, and the substrate is exposed to a germanium-silicon mixture under conditions selected to preferentially deposit a germanium-silicon alloy barrier layer on the exposed polysilicon layer.

Abstract: Disclosed is a prefetch execution unit, prefetch instruction buffer and a prefetch victim buffer which operate to optimize prefetching by recording a particular cache miss' history. To record cache misses, victimized (overwritten) lines and/or a prefetch tag are stored in a prefetch victim buffer. When the processor experiences a cache miss, it accesses the prefetch victim buffer to retrieve information relating to the prefetch victim. The prefetch execution unit then modifies the values of the additional field or fields and then stores the modified augmented prefetch instruction in the prefetch instruction buffer. The next time a prefetch instruction for the victimized lines is executed by the processor, the new values of the modified augmented prefetch instruction will dictate where the prefetch information is stored or what size increment it has. By continuous modification of the augmented prefetch instructions, eventually thrashing may be eliminated.

Abstract: This invention is directed to a lightweight concrete combination. The combination includes a lightweight concrete product having auxiliary structures, such as at least one fastener, embedded therein. The lightweight concrete product comprises (a) cement and (b) a lightweight additive material. The invention also relates to a method for using the lightweight concrete product, and to a method for producing the lightweight concrete combination.

Abstract: A data in/out channel control circuit for a semiconductor memory device with multi-bank structure includes a plurality of split banks each provided with memory cell arrays, each split bank having a plurality of bit line pairs and a sub in/out line pair connected through a column selection transistor pair, for efficiently connecting data from the bit line pairs to a global in/out line pair. The circuit enables transmission of only the data in a given block bank through the global in/out line pair and the sub in/out line pairs with bank selection information and block selection information.

Abstract: An electrostatic discharge structure of a semiconductor device is provided. The structure includes a semiconductor substrate doped with P-type impurities; an N-type well formed in a predetermined region of the semiconductor substrate; a P-type pocket well formed in a predetermined region of the N-type well; an N-type active guardline formed in the surface of the N-type well and doped to a concentration higher than that of the N-type well; a P-type active guardline formed in the surface of the P-type pocket well and doped to a concentration higher than that of the P-type pocket well; and an NMOS transistor formed in a surface of the P-type pocket well. Accordingly, even though a negative voltage due to electrostatic charge is temporarily applied to the drain region of the NMOS transistor, a malfunction of an internal circuitry formed in a P-type semiconductor substrate can be prevented.

Abstract: A semiconductor memory device uses three different power supply voltage levels including an internal IVcc, ground Vss and a boosted level Vpp more positive than the internal Vcc. A precharge control circuit in the memory device includes at least one NMOS transistor, at least one PMOS transistor and an output node having voltage values ranging from the IVcc either to Vss or to Vpp. The NMOS transistor acts as a loading transistor to the PMOS transistor and prevents latch-up in the PMOS transistor by maintaining IVcc below Vpp during the initial power set-up period of the memory device.

Abstract: An electro-convulsive therapy (ECT) system includes both hardware and software safety detectors and monitors, including a pulse generator that generates a pulse train of a plurality of pulses with parameters specified by the user. The safety monitors monitor these user-specified parameters as well as other important pulse parameters both during treatment of a patient and prior to treatment in order to ensure that the system is operating according to specification and, therefore, will not injure the patient. The pulse generator is responsive to the safety monitors in that if any of the safety detectors detect a parameter that is out of tolerance, the safety monitor disables the pulse generator so that no further pulses are delivered to the patient. The safety detectors detect plurality of pulse characteristics including pulse width, frequency, voltage, current, treatment duration, as well as energy.

Abstract: An SRAM, which includes a plurality of bit line pairs, a memory cell connected between each pair of the bit lines, and an address transition detection circuit for detecting transition of the externally applied address signal to generate a detection pulse signal, is provided with an improved bit line precharge circuit requiring only two transistors per bit line pair. The new precharge circuit is controlled by a bit line precharge control signal generator for generating a control signal determined by a ratio of impedances connected between a source voltage and ground voltage.

Abstract: A system for monitoring and configuring gaming devices interconnected over a high-speed network is disclosed. The system can support a file server, one or more floor controllers, one or more pit terminals, and other terminals all interconnected over the network. Each gaming device includes an electronic module which allows the gaming device to communicate with a floor controller over a current loop network. The electronic module includes a player tracking module and a data communication node. The player tracking module includes a card reader for detecting a player tracking card inserted therein which identifies the player. The data communication node communicates with both the floor controller and the gaming device. The data communication node communicates with the gaming device over a serial interface through which the data communication node transmits reconfiguration commands.

Abstract: A high density dimmer module controls four separate lighting circuits and provides adequate cooling while maintaining a form factor identical to conventional dimmer modules. The module includes circuit breakers arranged in stacks located adjacent to the front of the module. The circuit breaker stacks are spaced apart to allow cooling air to flow between, and to each side of, the circuit breakers. The air then flows past a power device and four toroidal inductors which are arranged behind and between the stacks. In a preferred embodiment, the module includes an input power connector positioned adjacent the rear periphery of the module chassis, first and second stacks of circuit breakers positioned adjacent the front periphery, four inductors arranged in an arcuate pattern behind the circuit breaker stacks, a power device located adjacent a sidewall of the chassis, and four output load connectors positioned adjacent the rear periphery.